Re: Are chips ... tilling pattern? magical seals?

On Sat, 6/20/2026 7:48 AM, Mr. Man-wai Chang wrote:
> On 6/20/2026 2:48 PM, Paul wrote:
>>
>> When you do that, you have to know the tiling pattern of cells
>> on the chip surface. A silicon chip may not have an ....
> 
> I Google-ed a bit about what you said about "tiling pattern of cells
> on the chip surface". So all chips are just drawing nano-fine lines on some special surfaces using special materia and light-etching machines? It's not the same as integrated circuits???
> 
> What you said is not very much from magicians drawing seals using magical wands!!! :)
> 
> 魔動王 - YouTube
> <https://www.youtube.com/watch?v=sdU8PHV5LF4>
> 

When you make DRAM or NAND flash, the elements have
to be laid down in the X,Y direction. And they are
not put in order. They're arranged to reduce
electrical interference.

They don't go like this.

     1 2 3 4 5
   1
   2
   3
   4
   5

It's a repeating pattern. After a small patch of x,y dots, the
pattern should repeat.

When you run memtest, it has some "pattern sensitivity" things
it tries to do. The layout of those DRAM cells, attempts to
prevent simple minded tests from finding the "sensitive" patterns.

And NAND flash does something like that too.

These things are orderly patterns, but they're arranged according
to estimates of electric fields around elements, and how best
to avoid spots where there would be too much interference. I have
not seen any pictures presented, to demonstrate exactly what the
patterns look like.

There are a number of patterns in electronics, that aren't power-of-two
any more. A lot of the former concepts of "what is easy to do",
have been thrown out the window.

   Paul