Re: IBM - New SUB-Nanometer STACKED Chip

On Wed, 7/1/2026 2:04 AM, c186282 wrote:
> On 6/30/26 19:28, rbowman wrote:
>> On Tue, 30 Jun 2026 16:27:24 +0100, The Natural Philosopher wrote:
>>
>>> "Transistor nodes have shrunk dramatically, with leading developers like
>>> IBM advancing into the sub-1 nanometre realm (e.g., 0.7-nanometer tech).
>>> However, absolute limits are rapidly approaching due to several factors:
>>
>> iirc terms like '5 nm process' no longer refer to any physical dimension
>> so I'm curious what the actual gate size is on 0.7 nm tech.
>>
>> IBM sold their fab lines to GlobalFoundries and their '7 nm' tech was
>> closer to Intel's 10 nm.
> 
>   Well, SEEMS like they've done the 1, or <1, nm
>   stacked chip.

You will need to see the dimensions of the whole thing,
to see which "chance" dimension is 1nm.

  https://newsroom.ibm.com/2026-06-25-ibm-debuts-worlds-first-sub-1-nanometer-chip-technology

     https://filecache.mediaroom.com/mr5mr_ibmnewsroom/201436/IBM-Research_TEM_4.jpg

The diagram here, is too hard to read. The FINFET is on the left. The Gate All Around
device in the center. The stacked P channel and N channel on the right.

  https://www.eetimes.com/ibm-shows-sub-1-nm-chips-targeting-production-in-5-years/

They talk here, of two wafers being bonded vertically. Which might
be how the scheme maintains a semblance of manufacturability. Imagine
an 18" (450mm" wafer, aligned at the atomic level.

  https://www.servethehome.com/ibm-outlines-sub-1nm-nanostack-transistor-technology/

    Paul