Re: IBM - New SUB-Nanometer STACKED Chip
c186282 <[email protected]>
| Newsgroups | comp.os.linux.misc |
|---|---|
| Organization | wokiesux |
| Message-ID | <[email protected]> |
On 6/28/26 14:09, Charlie Gibbs wrote: > On 2026-06-28, c186282 <[email protected]> wrote: > >> https://www.techspot.com/news/112907-ibm-unveils-sub-1-nanometer-chip-architecture-stacks.html >> >> IBM unveils sub-1-nanometer chip architecture that stacks 100 >> billion transistors onto a fingernail-sized processor >> >> . . . >> >> Pretty impressive ... and stacking two (three?) layers >> really packs a lot in. >> >> NOT sure how they deal with the HEAT in the stacked >> design. >> >> 100 billion ... how many in the i4004 ? > > Dunno - but I do remember that manufacturers hit a wall for > a while when trying to get below 1 micrometer. It took some > time before memory chips larger than 64K became available. Found it in WikiPedia ... 2300 transistors ! And yea, I remember how long it took them to significantly shrink things. "Stacked" chips have long been of interest to save real estate and signal path, but again not revealed how IBM has managed to cope with the heat dissipation issues. The sub-nanometer bit ... that IS a significant step. BUT, the smaller you make things, the more likely natural radiation and even quantum effects will sneakily change bits. We've pushed Moore further than I thought he could be, but ...