Re: IBM - New SUB-Nanometer STACKED Chip

On 30/06/2026 10:14, c186282 wrote:
> On 6/29/26 07:20, Mr. Man-wai Chang wrote:
>> On 6/29/2026 1:39 PM, c186282 wrote:
>>>
>>>     Amazed they were able to get this small - but do
>>>     expect a wall/seal is pretty much here. We're
>>>     talking kinda atomic dimensions now - nowhere else
>>>     to go using any conventional approaches. Anything
>>>     much further won't be 'electronics' as we know it,
>>>     some kind of weird quantum stuff.
>>>
>>>     STABLE deca-state logic maybe ?
>>
>> Can you fabricate 0.000000...0000000001 nm chips?
>>
>> Is zero the seal or wall? :)
> 
>    Um, pretty quick you get to ATOMS ... and, for any
>    normal electronics, that's IT.
> 
Actually the limit is a fair bit above atoms

GOOGLE AI
=========
"Transistor nodes have shrunk dramatically, with leading developers like 
IBM advancing into the sub-1 nanometre realm (e.g., 0.7-nanometer tech). 
However, absolute limits are rapidly approaching due to several factors:

     Quantum Tunnelling: At sizes measuring just a few atoms across, 
electrons no longer stay neatly in their channels. They start randomly 
leaking or tunnelling through insulation barriers, resulting in massive 
power loss and data corruption.

     Atomic Boundary: The absolute physical limit for a silicon 
semiconductor is effectively constrained by the size of the silicon 
crystal unit cell (about 0.54 nm).

      Heat Density: Shrinking transistors allows more components to be 
packed together, but it creates extreme heat concentrations. The 
challenge shifts from building them to keeping them cool without burning 
out£

.....

I note that google can't spall 'nanometre' OR 'tunnelling; correctly

...
-- 
Any fool can believe in principles -  and most of them do!