Re: IBM - New SUB-Nanometer STACKED Chip

On Sun, 28 Jun 2026 18:09:44 GMT, Charlie Gibbs wrote:

> Dunno - but I do remember that manufacturers hit a wall for a while
> when trying to get below 1 micrometer.

Part of the way past the barrier was, shall we say, redefining the
problem.

Down to, I’m not sure, maybe 100nm or a bit below, that measurement
was the actual feature size.

Nowadays, what the companies call a “1nm” process is still working
with transistors with dimensions more like 30nm; they are just
stacking them in layers to get an equivalent density to 1nm if you
were working only in two dimensions.