[PATCH] clk: mediatek: mt8188: fix top0 gate polarity

Gates in top0_cg_regs are active-high. The GATE_TOP0/GATE_TOP0E macros
set CLK_GATE_NO_SETCLR flags, which treat them as active-low. Enabling
the clock is currently disabling them.

Switch both macros to CLK_GATE_NO_SETCLR_INV to use the correct
active-high semantics.

Signed-off-by: Julien Stephan <[email protected]>
---
This was not detected before, because the top0 clocks were never used.
Some of them are part of the video pipeline needed to enable hdmi.
---
 drivers/clk/mediatek/clk-mt8188.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/clk/mediatek/clk-mt8188.c b/drivers/clk/mediatek/clk-mt8188.c
index eb98f7fdf6a..e0855da3bc1 100644
--- a/drivers/clk/mediatek/clk-mt8188.c
+++ b/drivers/clk/mediatek/clk-mt8188.c
@@ -1363,7 +1363,7 @@ static const struct mtk_gate_regs top1_cg_regs = {
 		.parent = _parent,				   \
 		.regs = &top0_cg_regs,				   \
 		.shift = _shift,				   \
-		.flags = CLK_GATE_NO_SETCLR | CLK_PARENT_TOPCKGEN, \
+		.flags = CLK_GATE_NO_SETCLR_INV | CLK_PARENT_TOPCKGEN, \
 	}
 
 #define GATE_TOP0E(_id, _parent, _shift) {			   \
@@ -1371,7 +1371,7 @@ static const struct mtk_gate_regs top1_cg_regs = {
 		.parent = _parent,				   \
 		.regs = &top0_cg_regs,				   \
 		.shift = _shift,				   \
-		.flags = CLK_GATE_NO_SETCLR | CLK_PARENT_EXT,	   \
+		.flags = CLK_GATE_NO_SETCLR_INV | CLK_PARENT_EXT,	   \
 	}
 
 #define GATE_TOP1(_id, _parent, _shift) {			       \

---
base-commit: 0890d2d1db70b581e10d39fb39537cff85f90fb3
change-id: 20260728-mt8188-clk-fix-top0-gate-polarity-82679bab4819

Best regards,
--  
Julien Stephan <[email protected]>