[PATCH 07/13] video: mediatek: add vdosys1 component

vdosys1 hosts the routing muxes (SEL_IN/SOUT) of the video pipeline
on some MediaTek SoCs, such as the MT8188. Configure the route from
the VPP merge output through the ETHDR mixer and the HDR back-end
down to DPI1.

Signed-off-by: Julien Stephan <[email protected]>
---
 drivers/video/mediatek/mtk_vdosys1_mt8188.c | 74 +++++++++++++++++++++++++++++
 drivers/video/mediatek/mtk_vdosys1_mt8188.h | 16 +++++++
 2 files changed, 90 insertions(+)

diff --git a/drivers/video/mediatek/mtk_vdosys1_mt8188.c b/drivers/video/mediatek/mtk_vdosys1_mt8188.c
new file mode 100644
index 00000000000..61d84d745af
--- /dev/null
+++ b/drivers/video/mediatek/mtk_vdosys1_mt8188.c
@@ -0,0 +1,74 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Mediatek MT8188 VDOSYS1 support
+ *
+ * Copyright (c) 2025 BayLibre, SAS.
+ * Author: Julien Stephan <[email protected]>
+ */
+
+#include <dm.h>
+
+#include "mtk_disp_comp.h"
+#include "mtk_vdosys1_mt8188.h"
+
+#define SUBDISP_DISP_DPI1_SEL_IN	0xF10
+#define SUBDISP_DISP_MERGE4_MOUT_SEL	0xF18
+#define SUBDISP_MIXER_IN3_SEL_IN	0xF2C
+#define SUBDISP_MIXER_OUT_SOUT_SEL	0xF34
+#define SUBDISP_MERGE2_ASYNC_SOUT_SEL	0xF48
+#define SUBDISP_MERGE4_ASYNC_SEL_IN	0xF50
+#define SUBDISP_MIXER_IN3_SOUT_SEL	0xF60
+#define SUBDISP_MIXER_SOUT_SEL_IN	0xF68
+
+#define OUTPUT_TO_MIXER_IN3_SEL		0x1
+#define INPUT_FROM_MERGE2_ASYNC_SOUT	0x1
+#define OUTPUT_TO_DISP_MIXER		0x0
+#define INPUT_FROM_DISP_MIXER		0x0
+#define OUTPUT_TO_HDR_VDO_BE0		0x0
+#define INPUT_FROM_HDR_VDO_BE0		0x0
+#define OUTPUT_TO_DPI1_SEL		0x4
+#define INPUT_FROM_VPP_MERGE4_MOUT	0x0
+
+void mtk_vdosys1_configure_hdmi(struct udevice *dev)
+{
+	/* MERGE2_ASYNC_SOUT --> MIXER_IN3_SEL */
+	mtk_disp_comp_write(dev, SUBDISP_MERGE2_ASYNC_SOUT_SEL,
+			    OUTPUT_TO_MIXER_IN3_SEL);
+	mtk_disp_comp_write(dev, SUBDISP_MIXER_IN3_SEL_IN,
+			    INPUT_FROM_MERGE2_ASYNC_SOUT);
+
+	/* MIXER_IN3_SOUT --> DISP_MIXER */
+	mtk_disp_comp_write(dev, SUBDISP_MIXER_IN3_SOUT_SEL,
+			    OUTPUT_TO_DISP_MIXER);
+
+	/* DISP_MIXER --> MIXER_SOUT_SEL */
+	mtk_disp_comp_write(dev, SUBDISP_MIXER_SOUT_SEL_IN,
+			    INPUT_FROM_DISP_MIXER);
+
+	/* MIXER_SOUT_SEL --> HDR_VDO_BE0 */
+	mtk_disp_comp_write(dev, SUBDISP_MIXER_OUT_SOUT_SEL,
+			    OUTPUT_TO_HDR_VDO_BE0);
+
+	/* HDR_VDO_BE0 --> MERGE4_ASYNC_SEL */
+	mtk_disp_comp_write(dev, SUBDISP_MERGE4_ASYNC_SEL_IN,
+			    INPUT_FROM_HDR_VDO_BE0);
+
+	/* MERGE4_MOUT_SEL --> DPI1_SEL */
+	mtk_disp_comp_write(dev, SUBDISP_DISP_MERGE4_MOUT_SEL,
+			    OUTPUT_TO_DPI1_SEL);
+	mtk_disp_comp_write(dev, SUBDISP_DISP_DPI1_SEL_IN,
+			    INPUT_FROM_VPP_MERGE4_MOUT);
+}
+
+static const struct udevice_id mtk_vdosys1_ids[] = {
+	{ .compatible = "mediatek,mt8188-vdosys1-pipeline" },
+	{}
+};
+
+U_BOOT_DRIVER(mtk_vdosys1) = {
+	.name	   = "mtk_vdosys1",
+	.id	   = UCLASS_MISC,
+	.of_match  = mtk_vdosys1_ids,
+	.probe	   = mtk_disp_comp_probe,
+	.priv_auto = sizeof(struct mtk_disp_comp_priv),
+};
diff --git a/drivers/video/mediatek/mtk_vdosys1_mt8188.h b/drivers/video/mediatek/mtk_vdosys1_mt8188.h
new file mode 100644
index 00000000000..e388a068343
--- /dev/null
+++ b/drivers/video/mediatek/mtk_vdosys1_mt8188.h
@@ -0,0 +1,16 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Mediatek MT8188 VDOSYS1 Support
+ *
+ * Copyright (c) 2025 BayLibre, SAS.
+ * Author: Julien Stephan <[email protected]>
+ */
+
+#ifndef _MTK_VDOSYS1_MT8188_H
+#define _MTK_VDOSYS1_MT8188_H
+
+struct udevice;
+
+void mtk_vdosys1_configure_hdmi(struct udevice *dev);
+
+#endif

-- 
2.54.0