Re: [PATCH] clk: mediatek: mt8188: fix top0 gate polarity

David Lechner <[email protected]>
Newsgroups gmane.comp.boot-loaders.u-boot
Message-ID <[email protected]> 
On 7/28/26 7:28 AM, Julien Stephan wrote:
> Gates in top0_cg_regs are active-high. The GATE_TOP0/GATE_TOP0E macros
> set CLK_GATE_NO_SETCLR flags, which treat them as active-low. Enabling
> the clock is currently disabling them.
> 
> Switch both macros to CLK_GATE_NO_SETCLR_INV to use the correct
> active-high semantics.
> 

Can you reply with a Fixes: tag since this is fixing a bug? (No need
to resend.)

> Signed-off-by: Julien Stephan <[email protected]>
> ---
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