Re: [PATCH] clk: mediatek: mt8188: fix top0 gate polarity

Julien Stephan <[email protected]>
Newsgroups gmane.comp.boot-loaders.u-boot
Message-ID <CAEHHSvaSjwn9POS_RPzPsN6sH_VOAD2z0ncOWRzt=_t=0oJrNw@mail.gmail.com> 
Le mar. 28 juil. 2026 à 16:12, David Lechner <[email protected]> a écrit :
>
> On 7/28/26 7:28 AM, Julien Stephan wrote:
> > Gates in top0_cg_regs are active-high. The GATE_TOP0/GATE_TOP0E macros
> > set CLK_GATE_NO_SETCLR flags, which treat them as active-low. Enabling
> > the clock is currently disabling them.
> >
> > Switch both macros to CLK_GATE_NO_SETCLR_INV to use the correct
> > active-high semantics.
> >
>
> Can you reply with a Fixes: tag since this is fixing a bug? (No need
> to resend.)
>

Fixes: 11f3cc46322a ("clk: mediatek: add MT8188 clock driver")

> > Signed-off-by: Julien Stephan <[email protected]>
> > ---
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