[PATCH 16/17] ARM: dts: r9a06g032-rzn1-snarc: enable new drivers
Ralph Siemsen <[email protected]> Fri, 31 Jul 2026 12:33:45 -0400
| Newsgroups | gmane.comp.boot-loaders.u-boot |
|---|---|
| Message-ID | <[email protected]> |
Add pinmux and enable newly added drivers: - MMC (SDIO) - QSPI flash - NAND flash - USB controller - GPIO - Ethernet (designware) - A5PSW ethernet switch - MIIC media converter Signed-off-by: Ralph Siemsen <[email protected]> --- arch/arm/dts/r9a06g032-rzn1-snarc.dts | 390 ++++++++++++++++++++++++++++++++++ 1 file changed, 390 insertions(+) diff --git a/arch/arm/dts/r9a06g032-rzn1-snarc.dts b/arch/arm/dts/r9a06g032-rzn1-snarc.dts index 7de8ee15ef3..c05dc3346ff 100644 --- a/arch/arm/dts/r9a06g032-rzn1-snarc.dts +++ b/arch/arm/dts/r9a06g032-rzn1-snarc.dts @@ -7,6 +7,7 @@ /dts-v1/; +#include <dt-bindings/gpio/gpio.h> #include <dt-bindings/pinctrl/rzn1-pinctrl.h> #include "r9a06g032.dtsi" @@ -73,9 +74,262 @@ }; }; +&gpio0 { + pinctrl-0 = <&pins_gpio0>; + pinctrl-names = "default"; + status = "okay"; +}; + +&gpio1 { + pinctrl-0 = <&pins_gpio1>; + pinctrl-names = "default"; + status = "okay"; +}; + +&gpio2 { + pinctrl-0 = <&pins_gpio2>; + pinctrl-names = "default"; + status = "okay"; +}; + +&gmac2 { + status = "okay"; + + phy-connection-type = "rgmii-id"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + }; + + fixed-link { + full-duplex; + speed = <1000>; + }; +}; + +ð_miic { + status = "okay"; +}; + +&mii_conv1 { + status = "okay"; +}; + +&mii_conv2 { + status = "okay"; +}; + +&mii_conv3 { + status = "okay"; +}; + +&mii_conv4 { + status = "okay"; +}; + +&mii_conv5 { + status = "okay"; +}; + +&switch { + pinctrl-0 = <&pins_eth3>, <&pins_eth4>, <&pins_mdio1>; + pinctrl-names = "default"; + status = "okay"; + + phy-reset-gpios = <&gpio2a 26 GPIO_ACTIVE_LOW>; + phy-reset-duration = <15>; + + dsa,member = <0 0>; + + syscon = <&plat_regs>; + + mdio { + clock-frequency = <2500000>; + + #address-cells = <1>; + #size-cells = <0>; + + switch0phy4: ethernet-phy@4 { + reg = <4>; + }; + + switch0phy5: ethernet-phy@5 { + reg = <5>; + }; + }; +}; + +&switch_port0 { + label = "end0"; + phy-mode = "rgmii-id"; + phy-handle = <&switch0phy5>; + status = "okay"; +}; + +&switch_port1 { + label = "end1"; + phy-mode = "rgmii-id"; + phy-handle = <&switch0phy4>; + status = "okay"; +}; + +&switch_port4 { + /* Upstream to GMAC2 */ + status = "okay"; +}; + &pinctrl { status = "okay"; + pins_eth3: pins_eth3 { + pinmux = < + RZN1_PINMUX(36, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII) /* ETH3_TXCLK */ + RZN1_PINMUX(37, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII) /* ETH3_TXD[0] */ + RZN1_PINMUX(38, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII) /* ETH3_TXD[1] */ + RZN1_PINMUX(39, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII) /* ETH3_TXD[2] */ + RZN1_PINMUX(40, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII) /* ETH3_TXD[3] */ + RZN1_PINMUX(41, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII) /* ETH3_TXEN */ + RZN1_PINMUX(42, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII) /* ETH3_RXCLK */ + RZN1_PINMUX(43, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII) /* ETH3_RXD[0] */ + RZN1_PINMUX(44, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII) /* ETH3_RXD[1] */ + RZN1_PINMUX(45, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII) /* ETH3_RXD[2] */ + RZN1_PINMUX(46, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII) /* ETH3_RXD[3] */ + RZN1_PINMUX(47, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII) /* ETH3_RXDV */ + >; + bias-disable; + drive-strength = <6>; + }; + + pins_eth4: pins_eth4 { + pinmux = < + RZN1_PINMUX(48, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII) /* ETH4_TXCLK */ + RZN1_PINMUX(49, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII) /* ETH4_TXD[0] */ + RZN1_PINMUX(50, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII) /* ETH4_TXD[1] */ + RZN1_PINMUX(51, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII) /* ETH4_TXD[2] */ + RZN1_PINMUX(52, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII) /* ETH4_TXD[3] */ + RZN1_PINMUX(53, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII) /* ETH4_TXEN */ + RZN1_PINMUX(54, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII) /* ETH4_RXCLK */ + RZN1_PINMUX(55, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII) /* ETH4_RXD[0] */ + RZN1_PINMUX(56, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII) /* ETH4_RXD[1] */ + RZN1_PINMUX(57, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII) /* ETH4_RXD[2] */ + RZN1_PINMUX(58, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII) /* ETH4_RXD[3] */ + RZN1_PINMUX(59, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII) /* ETH4_RXDV */ + >; + bias-disable; + drive-strength = <6>; + }; + + pins_gpio0: pins_gpio0 { + pinmux = < + RZN1_PINMUX(13, RZN1_FUNC_GPIO) /* GPIO0B[7] */ + RZN1_PINMUX(14, RZN1_FUNC_GPIO) /* GPIO0B[8] */ + RZN1_PINMUX(15, RZN1_FUNC_GPIO) /* GPIO0A[6] */ + RZN1_PINMUX(16, RZN1_FUNC_GPIO) /* GPIO0A[7] */ + RZN1_PINMUX(17, RZN1_FUNC_GPIO) /* GPIO0B[9] */ + RZN1_PINMUX(18, RZN1_FUNC_GPIO) /* GPIO0B[10] */ + RZN1_PINMUX(22, RZN1_FUNC_GPIO) /* GPIO0A[9] */ + RZN1_PINMUX(23, RZN1_FUNC_GPIO) /* GPIO0B[13] */ + >; + drive-strength = <6>; + bias-disable; + + pins_gpio0_pullup { + pinmux = < + RZN1_PINMUX(25, RZN1_FUNC_GPIO) /* GPIO0B[14] - A70CI_EN_N */ + RZN1_PINMUX(26, RZN1_FUNC_GPIO) /* GPIO0B[15] - A71CH_EN_N */ + RZN1_PINMUX(27, RZN1_FUNC_GPIO) /* GPIO0A[11] - TRUST_M_EN_N */ + RZN1_PINMUX(28, RZN1_FUNC_GPIO) /* GPIO0A[12] - TRUST_X_EN_N */ + RZN1_PINMUX(32, RZN1_FUNC_GPIO) /* GPIO0B[19] - STMA100_EN_N*/ + >; + drive-strength = <6>; + bias-pull-up; + }; + + }; + + pins_gpio1: pins_gpio1 { + pinmux = < + RZN1_PINMUX(108, RZN1_FUNC_GPIO) /* GPIO1A[18] - for SPI1_SS_N[0] */ + RZN1_PINMUX(109, RZN1_FUNC_GPIO) /* GPIO1A[19] - for SPI0_SS_N[1] */ + RZN1_PINMUX(110, RZN1_FUNC_GPIO) /* GPIO1A[20] - for SPI0_SS_N[2] */ + RZN1_PINMUX(114, RZN1_FUNC_GPIO) /* GPIO1A[24] - for SPI0_SS_N[0] */ + >; + }; + + pins_gpio2: pins_gpio2 { + pinmux = < + RZN1_PINMUX(147, RZN1_FUNC_GPIO) /* Eth4 IRQ (GPIO2A[25]) */ + RZN1_PINMUX(148, RZN1_FUNC_GPIO) /* Touch IRQ (GPIO2A[26]) */ + RZN1_PINMUX(149, RZN1_FUNC_GPIO) /* Eth5 IRQ (GPIO2A[27]) */ + >; + }; + + pins_mdio1: pins_mdio1 { + pinmux = < + RZN1_PINMUX(152, RZN1_FUNC_ETH_MDIO) /* MDIO1_MDC */ + RZN1_PINMUX(153, RZN1_FUNC_ETH_MDIO) /* MDIO1_MDIO */ + RZN1_PINMUX(171, RZN1_FUNC_MDIO1_SWITCH) /* MDIO1_MUX_SWITCH */ + >; + }; + + pins_nand: pins_nand { + pinmux = < + RZN1_PINMUX(80, RZN1_FUNC_CLK_ETH_NAND) /* NAND_ALE */ + RZN1_PINMUX(81, RZN1_FUNC_CLK_ETH_NAND) /* NAND_CLE */ + RZN1_PINMUX(82, RZN1_FUNC_CLK_ETH_NAND) /* NAND_WE_N */ + RZN1_PINMUX(83, RZN1_FUNC_CLK_ETH_NAND) /* NAND_RE_N */ + RZN1_PINMUX(84, RZN1_FUNC_CLK_ETH_NAND) /* NAND_IO[0] */ + RZN1_PINMUX(85, RZN1_FUNC_CLK_ETH_NAND) /* NAND_IO[1] */ + RZN1_PINMUX(86, RZN1_FUNC_CLK_ETH_NAND) /* NAND_IO[2] */ + RZN1_PINMUX(87, RZN1_FUNC_CLK_ETH_NAND) /* NAND_IO[3] */ + RZN1_PINMUX(88, RZN1_FUNC_CLK_ETH_NAND) /* NAND_IO[4] */ + RZN1_PINMUX(89, RZN1_FUNC_CLK_ETH_NAND) /* NAND_IO[5] */ + RZN1_PINMUX(90, RZN1_FUNC_CLK_ETH_NAND) /* NAND_IO[6] */ + RZN1_PINMUX(91, RZN1_FUNC_CLK_ETH_NAND) /* NAND_IO[7] */ + RZN1_PINMUX(92, RZN1_FUNC_CLK_ETH_NAND) /* NAND_CE_N[0] */ + RZN1_PINMUX(93, RZN1_FUNC_CLK_ETH_NAND) /* NAND_WP_N[0] */ + RZN1_PINMUX(94, RZN1_FUNC_CLK_ETH_NAND) /* NAND_RYBY_N[0] */ + >; + }; + + pins_qspi0: pins_qspi0 { + pinmux = < + RZN1_PINMUX(74, RZN1_FUNC_QSPI) /* QSPI0_CS_N[0] */ + RZN1_PINMUX(75, RZN1_FUNC_QSPI) /* QSPI0_IO[3] */ + RZN1_PINMUX(76, RZN1_FUNC_QSPI) /* QSPI0_IO[2] */ + RZN1_PINMUX(77, RZN1_FUNC_QSPI) /* QSPI0_IO[1] */ + RZN1_PINMUX(78, RZN1_FUNC_QSPI) /* QSPI0_IO[0] */ + RZN1_PINMUX(79, RZN1_FUNC_QSPI) /* QSPI0_CLK */ + >; + bias-disable; + }; + + pins_sdio1: pins_sdio1 { + pinmux = < + RZN1_PINMUX(95, RZN1_FUNC_SDIO) /* SDIO0_CMD */ + RZN1_PINMUX(97, RZN1_FUNC_SDIO) /* SDIO0_IO[0] */ + RZN1_PINMUX(98, RZN1_FUNC_SDIO) /* SDIO0_IO[1] */ + RZN1_PINMUX(99, RZN1_FUNC_SDIO) /* SDIO0_IO[2] */ + RZN1_PINMUX(100, RZN1_FUNC_SDIO) /* SDIO0_IO[3] */ + >; + + pins_sdio1_clk: pins_sdio1_clk { + pinmux = < + RZN1_PINMUX(96, RZN1_FUNC_SDIO) /* SDIO0_CLK */ + >; + drive-strength = <12>; + }; + + pins_sdio1_cd_wp: pins_sdio1_cd_wp { + pinmux = < + RZN1_PINMUX(101, RZN1_FUNC_SDIO_E) /* SDIO0_CD_N */ + RZN1_PINMUX(102, RZN1_FUNC_SDIO_E) /* SDIO0_WP */ + >; + bias-pull-down; + }; + }; + pins_uart0: pins_uart0 { pinmux = < RZN1_PINMUX(103, RZN1_FUNC_UART0_I) /* UART0_TXD */ @@ -83,6 +337,142 @@ >; bias-disable; }; + + pins_usb: pins_usb { + pins_usb_pdown { + pinmux = < + RZN1_PINMUX(119, RZN1_FUNC_USB) /* USB_PPON[1] */ + RZN1_PINMUX(121, RZN1_FUNC_USB) /* USB_PPON[2] */ + >; + drive-strength = <4>; + bias-pull-down; + }; + + pins_usb_pup { + pinmux = < + RZN1_PINMUX(120, RZN1_FUNC_USB) /* USB_OC[1] */ + RZN1_PINMUX(122, RZN1_FUNC_USB) /* USB_OC[2] */ + >; + drive-strength = <4>; + bias-pull-up; + }; + }; +}; + +&nand_controller { + pinctrl-0 = <&pins_nand>; + pinctrl-names = "default"; + status = "okay"; + + oob-reserved = <8>; + nand@0 { + label = "nand"; + reg = <0>; + + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + /* 512MB */ + label = "nand:ubi0"; + reg = <0x0000000 0>; + }; + }; +}; + +&qspi0 { + pinctrl-0 = <&pins_qspi0>; + pinctrl-names = "default"; + status = "okay"; + + flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <62500000>; + spi-cpha; + spi-cpol; + spi-rx-bus-width = <4>; + + partition@0 { + /* 256KB */ + label = "qspi0:spl"; + reg = <0x00000000 0x00040000>; + }; + partition@1 { + /* 256KB */ + label = "qspi0:unused_mtd3"; + reg = <0x00040000 0x00040000>; + }; + partition@2 { + /* 256KB */ + label = "qspi0:configcms"; + reg = <0x00080000 0x00040000>; + }; + partition@3 { + /* 256KB */ + label = "qspi0:unused_mtd5"; + reg = <0x000C0000 0x00040000>; + }; + partition@4{ + /* 256KB */ + label = "qspi0:env"; + reg = <0x00100000 0x00040000>; + }; + partition@5 { + /* 1MB */ + label = "qspi0:unused_mtd7"; + reg = <0x00140000 0x00100000>; + }; + partition@6 { + /* 1MB */ + label = "qspi0:uboot0fit"; + reg = <0x00240000 0x00100000>; + }; + partition@7 { + /* 1MB */ + label = "qspi0:uboot1fit"; + reg = <0x00340000 0x00100000>; + }; + partition@8 { + /* 1MB */ + label = "qspi0:tosfit0"; + reg = <0x00440000 0x00100000>; + }; + partition@9 { + /* 1MB */ + label = "qspi0:tosfit1"; + reg = <0x00540000 0x00100000>; + }; + partition@10 { + /* 1MB */ + label = "qspi0:cm3fit0"; + reg = <0x00640000 0x00100000>; + }; + partition@11 { + /* 1MB */ + label = "qspi0:cm3fit1"; + reg = <0x00740000 0x00100000>; + }; + partition@12 { + /* Remaining */ + label = "qspi0:data"; + reg = <0x00840000 0>; + }; + }; +}; + +&sdio1 { + pinctrl-0 = <&pins_sdio1>; + pinctrl-names = "default"; + status = "okay"; +}; + +&udc { + pinctrl-0 = <&pins_usb>; + pinctrl-names = "default"; + status = "okay"; }; &uart0 { -- 2.55.0