[PATCH 1/2] mtd: spi-nor-ids: Add variant of mt25qu256a chip

The current mt25qu256a entry has a JEDEC ID with an extended device ID
byte of 0x44. A variant of this chip this (model mt25qu256aba1ew9), has
an extended device ID byte of 0x40. The current JEDEC ID parsing code
incorrectly detects this as an n25q256ax1, which results in 4 byte
read/write opcodes not being used for this chip even though it supports
it.

According to Page 34 in the datasheet [1], the differences in the JEDEC
ID (Bit 3 in the Extended Device ID Data) correspond to whether Pin 1
functions as a Hold or Reset pin. This shouldn't affect any
functionality in U-Boot's communication with the chip.

Document this chip and it's JEDEC ID so that U-Boot uses 4 byte opcodes
for this chip.

[1] https://www.mouser.com/catalog/specsheets/micron%20technology_mict-s-a0001400588-1.pdf

Signed-off-by: Anirudh Srinivasan <[email protected]>

---
The differences in the functionality of Pin 1 (Hold/Reset) also reflect
in the model number of the flash chip, as per Page 2 of the datasheet.
The existing entry in U-Boot (0x44, Pin 1 reset), should have a model
number mt25qu256aba3xxx, whereas the chip I'm trying to document (0x40,
Pin 1 hold) should have a model number mt25qu256aba1xxx. I didn't want
to change the name of the existing entry in U-Boot, so I've left it as
is.
---
 drivers/mtd/spi/spi-nor-ids.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/mtd/spi/spi-nor-ids.c b/drivers/mtd/spi/spi-nor-ids.c
index 31a2ba49a87..ed43104bf53 100644
--- a/drivers/mtd/spi/spi-nor-ids.c
+++ b/drivers/mtd/spi/spi-nor-ids.c
@@ -416,6 +416,8 @@ const struct flash_info spi_nor_ids[] = {
 	{ INFO6("mt25ql256a",    0x20ba19, 0x104400, 64 * 1024,  512, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES | USE_FSR) },
 	{ INFO("n25q256a",    0x20ba19, 0, 64 * 1024,  512, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_FSR) },
 	{ INFO6("mt25qu256a",  0x20bb19, 0x104400, 64 * 1024,  512, SECT_4K | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES | USE_FSR) },
+	{ INFO6("mt25qu256aba1",  0x20bb19, 0x104000, 64 * 1024,  512,
+	  SECT_4K | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES | USE_FSR) },
 	{ INFO("n25q256ax1",  0x20bb19, 0, 64 * 1024,  512, SECT_4K | SPI_NOR_QUAD_READ | USE_FSR) },
 	{ INFO("mt25qu128ab", 0x20bb18, 0, 64 * 1024,  256, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ) },
 	{ INFO6("mt25qu512a",  0x20bb20, 0x104400, 64 * 1024, 1024,

-- 
2.43.0