[PATCH 2/4] clk: rockchip: rk3588: Always init clocks in SPL build

The CPU PLLs and SPLL are only initialized in SPL on RK3588.

Ensure clock driver is always probed after bind for SPL builds to
initialize core PLLs and clocks in SPL phase on RK3588.

Signed-off-by: Jonas Karlman <[email protected]>
---
 drivers/clk/rockchip/clk_rk3588.c | 14 ++++++++++++++
 1 file changed, 14 insertions(+)

diff --git a/drivers/clk/rockchip/clk_rk3588.c b/drivers/clk/rockchip/clk_rk3588.c
index 5236c3fa985e..5313457aec92 100644
--- a/drivers/clk/rockchip/clk_rk3588.c
+++ b/drivers/clk/rockchip/clk_rk3588.c
@@ -2004,6 +2004,10 @@ static int rk3588_clk_bind(struct udevice *dev)
 	struct udevice *sys_child;
 	struct sysreset_reg *priv;
 
+	/* Ensure clocks are initialized after bind in SPL build */
+	if (IS_ENABLED(CONFIG_SPL_BUILD))
+		dev_or_flags(dev, DM_FLAG_PROBE_AFTER_BIND);
+
 	/* The reset driver does not have a device node, so bind it here */
 	ret = device_bind_driver(dev, "rockchip_sysreset", "sysreset",
 				 &sys_child);
@@ -2133,6 +2137,15 @@ static int rk3588_scru_clk_probe(struct udevice *dev)
 	return 0;
 }
 
+static int rk3588_scru_clk_bind(struct udevice *dev)
+{
+	/* Ensure clocks are initialized after bind in SPL build */
+	if (IS_ENABLED(CONFIG_SPL_BUILD))
+		dev_or_flags(dev, DM_FLAG_PROBE_AFTER_BIND);
+
+	return 0;
+}
+
 static const struct clk_ops rk3588_scru_clk_ops = {
 	.get_rate = rk3588_scru_clk_get_rate,
 	.set_rate = rk3588_scru_clk_set_rate,
@@ -2142,6 +2155,7 @@ U_BOOT_DRIVER(rockchip_rk3588_scru) = {
 	.name	= "rockchip_rk3588_scru",
 	.id	= UCLASS_CLK,
 	.ops	= &rk3588_scru_clk_ops,
+	.bind	= rk3588_scru_clk_bind,
 	.probe	= rk3588_scru_clk_probe,
 };
 
-- 
2.54.0