Re: [PATCH 01/15] clk: rockchip: pll: Fix double use of postdiv1

Hi Jonas,

On 7/30/26 4:12 PM, Jonas Karlman wrote:
> The possible frac_rate part of rk3036_pll plls is divided two times by
> postdiv1 instead of both postdiv1 and postdiv2 as the integer part. Fix
> this by using postdiv2 in the second do_div() call.
> 

I... cannot find which SoC(s) actually makes use of that function. It's 
only called when pll->type = rk3036 (which is 0, so anything that 
doesn't explicitly set ->type will have its type be rk3036), but all the 
drivers declaring a rockchip_pll_clock array specify something that 
isn't rk3036. So... is this dead code or what did I miss :)?

Where did you get the formula also, I couldn't quickly find a publicly 
leaked TRM for RK3036 (and since I couldn't figure out which SoC(s) use 
the same formula...).

Cheers,
Quentin