Re: [PATCH 04/15] clk: rockchip: pll: Use PLL_FIXED_MODE flag on rk3588/rk3576 plls

Hi Jonas,

On 7/30/26 4:12 PM, Jonas Karlman wrote:
> The PPLL of RK3588 and RK3576 does not have a pll mode reg to switch
> between slow, deep slow or normal mode.
> 
> Extend support for use of the PLL_FIXED_MODE flag to the rk3588_pll type
> and update the PPLL to use this flag to signal that it does not need to
> switch to slow mode before the rate is changed.
> 

At a glance, it seems the Linux kernel is doing something different. 
Instead, it checks whether the current mode is normal (0x1) if not, then 
it sets it to slow while changing the rate (and then revert back to 
normal mode). I'm assuming they rely on undocumented registers (the PLL 
that don't have a slow mode for example) returning zeroes (i.e., slow 
mode) so they don't do this dance for when slow mode (or undocumented 
registers) is set. Did you send patches to the Linux kernel for this, 
are you planning to maybe?

This change here seems fine to me but we continue diverging from design 
decisions made in the Linux kernel (which aren't necessarily correct). 
Anyway:

Reviewed-by: Quentin Schulz <[email protected]>

Thanks!
Quentin