[PATCH v2 1/4] x86: qemu: Describe pflash

QEMU pflash is mapped just below 4GiB. Describe it as a cfi-flash
node so the MTD subsystem can probe it. When a flash device is not
exposed to the guest by QEMU, the address is still backed by ROM, so
we'll just see no flash found rather than faulting.

Signed-off-by: Elliot Berman <[email protected]>
---
 arch/x86/dts/pflash.dtsi         | 18 ++++++++++++++++++
 arch/x86/dts/qemu-x86_i440fx.dts |  1 +
 arch/x86/dts/qemu-x86_q35.dts    |  1 +
 3 files changed, 20 insertions(+)

diff --git a/arch/x86/dts/pflash.dtsi b/arch/x86/dts/pflash.dtsi
new file mode 100644
index 00000000000..9d172ee51d4
--- /dev/null
+++ b/arch/x86/dts/pflash.dtsi
@@ -0,0 +1,18 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * QEMU pflash (CFI NOR) mapped just below 4GiB. QEMU aligns the pflash so
+ * that it ends at the top of the 32-bit address space.
+ * https://gitlab.com/qemu-project/qemu/-/blob/v11.0.3/hw/i386/pc_sysfw.c?ref_type=tags#L128
+ * The actual pflash start is driven by QEMU using, based on the size of U-Boot ROM size.
+ * We assume u-boot is loaded as the -pflash/-bios option
+ */
+
+#define ROM_START (0x100000000 - CONFIG_ROM_SIZE)
+
+/ {
+	pflash {
+		compatible = "cfi-flash";
+		reg = <ROM_START CONFIG_ROM_SIZE>;
+		bank-width = <1>;
+	};
+};
diff --git a/arch/x86/dts/qemu-x86_i440fx.dts b/arch/x86/dts/qemu-x86_i440fx.dts
index 3bb2f121de3..7f9ff6b1cfb 100644
--- a/arch/x86/dts/qemu-x86_i440fx.dts
+++ b/arch/x86/dts/qemu-x86_i440fx.dts
@@ -15,6 +15,7 @@
 
 #include "tsc_timer.dtsi"
 #include "smbios.dtsi"
+#include "pflash.dtsi"
 
 / {
 	model = "QEMU x86 (I440FX)";
diff --git a/arch/x86/dts/qemu-x86_q35.dts b/arch/x86/dts/qemu-x86_q35.dts
index 63931cd6dd9..24c93c45677 100644
--- a/arch/x86/dts/qemu-x86_q35.dts
+++ b/arch/x86/dts/qemu-x86_q35.dts
@@ -25,6 +25,7 @@
 
 #include "tsc_timer.dtsi"
 #include "smbios.dtsi"
+#include "pflash.dtsi"
 
 / {
 	model = "QEMU x86 (Q35)";

-- 
2.54.0