[PATCH v2 1/3] spi: cadence_qspi: enable all clocks

On certain devices (such as Renesas RZ/N1) it is necessary to
enable the clock(s) before accessing the QSPI controller registers.

As there can be multiple clocks, use clk_get_bulk() to obtain clock(s)
and clk_enable_bulk() to turn them on. Warn if clk_enable_bulk() fails,
but keep going so as not to break existing users.

As before, it is assumed that the first clock is the reference clock,
so the order in the devicetree matters.

Signed-off-by: Ralph Siemsen <[email protected]>
---
Changes in v2:
- patch was split from the series "Renesas RZ/N1 additional drivers"
  https://lore.kernel.org/u-boot/[email protected]/
- move clock enable before clk_get_rate()
- handle multiple clocks using clk_get_bulk() and clk_enable_bulk()
---
 drivers/spi/cadence_qspi.c | 10 +++++++---
 1 file changed, 7 insertions(+), 3 deletions(-)

diff --git a/drivers/spi/cadence_qspi.c b/drivers/spi/cadence_qspi.c
index 984d4a39ded..0f70493dea4 100644
--- a/drivers/spi/cadence_qspi.c
+++ b/drivers/spi/cadence_qspi.c
@@ -208,7 +208,7 @@ static int cadence_spi_probe(struct udevice *bus)
 {
 	struct cadence_spi_plat *plat = dev_get_plat(bus);
 	struct cadence_spi_priv *priv = dev_get_priv(bus);
-	struct clk clk;
+	struct clk_bulk clks;
 	int ret;
 
 	priv->regbase		= plat->regbase;
@@ -240,7 +240,7 @@ static int cadence_spi_probe(struct udevice *bus)
 				  ZYNQMP_PM_REQUEST_ACK_NO, 0, 0, NULL);
 
 	if (priv->ref_clk_hz == 0) {
-		ret = clk_get_by_index(bus, 0, &clk);
+		ret = clk_get_bulk(bus, &clks);
 		if (ret) {
 #ifdef CONFIG_HAS_CQSPI_REF_CLK
 			priv->ref_clk_hz = CONFIG_CQSPI_REF_CLK;
@@ -250,7 +250,11 @@ static int cadence_spi_probe(struct udevice *bus)
 			return ret;
 #endif
 		} else {
-			priv->ref_clk_hz = clk_get_rate(&clk);
+			ret = clk_enable_bulk(&clks);
+			if (ret)
+				dev_warn(bus, "failed clk_enable_bulk\n");
+
+			priv->ref_clk_hz = clk_get_rate(&clks.clks[0]);
 			if (IS_ERR_VALUE(priv->ref_clk_hz))
 				return priv->ref_clk_hz;
 		}

-- 
2.55.0