Re: [GIT PULL] SoCFPGA updates for next (2026-08-17)

On Mon, Aug 17, 2026 at 11:29:50AM +0800, Chee, Tien Fong via U-Boot wrote:

> Hi Tom,
> 
> Please pull the following SoCFPGA updates for next.
> 
> The following changes since commit 527115ef6783cec49e5610c523c124b399011361:
> 
>   pylibfdt: Replace removed SWIG Python 2 compatibility macros (2026-08-13
> 10:12:41 -0600)
> 
> are available in the Git repository at:
> 
>   https://source.denx.de/u-boot/custodians/u-boot-socfpga.git
> tags/u-boot-socfpga-next-20260817
> 
> for you to fetch changes up to 96ba02bb50016fe70d2fb087d7698c56793f7d46:
> 
>   arm: socfpga: Improve handoff prepare on SoCFPGA (2026-07-29 00:36:13
> +0800)

I know CI doesn't fail on this, so I only saw it in my build logs:
       arm:  w+   socfpga_de10_nano
+(socfpga_de10_nano)
+(socfpga_de10_nano) WARNING: unmet direct dependencies detected for DESIGNWARE_WATCHDOG
+(socfpga_de10_nano)   Depends on [n]: WDT [=n]
+(socfpga_de10_nano)   Selected by [y]:
+(socfpga_de10_nano)   - ARCH_SOCFPGA_CYCLONE5 [=y] && ARM [=y] && ARCH_SOCFPGA [=y] && !TARGET_SOCFPGA_TERASIC_SOCKIT [=n] && !TARGET_SOCFPGA_EBV_SOCRATES [=n] && !TARGET_SOCFPGA_SOFTING_VINING_FPGA [=n]

That needs to be fixed.

[snip]
> ---
> 
> This pull request updates SoCFPGA platforms with Stratix 10 and N5X
> driver-model
> conversions, DDR robustness fixes, Agilex5 storage and DT updates, and
> Gen5/Arria10
> maintenance.
> 
> Stratix 10
> Switch to the upstream Linux DT, combine boot-flash defconfigs, and move
> firmware
> register settings into the device tree. Enable the system manager driver,
> refactor
> the S10 clock driver, exclude S10 from legacy MMC clkmgr address lookup, and
> improve SPL data save/restore and watchdog support.
> 
> N5X
> Enable the system manager driver and switch firewall setup to driver model.
> Adopt the upstream Linux DT, update GMAC nodes, consolidate ATF/VAB
> defconfigs,
> and use common SoC64 environment settings. Enable CMD_MTD and ISSI QSPI,
> split
> the reset manager into common and platform-family parts, and drop the kernel
> node from binman for the non-VAB flow.
> 
> DDR and memory
> Add ECC DRAM scrubbing and DRAM size checking for Gen5/Arria10,
> secure-region
> support for the ATF flow, a delay before MBRDADDR writes, and a data-cache
> flush
> fix. Use dev_read_addr_index_ptr() in the DDR driver.
> 
> Agilex / Agilex5
> Add an Agilex eMMC device tree, enable 8-bit eMMC, restrict watchdog0
> autostart,
> set DTB filename and kernel-node removal for non-secure boot, disable gmac2
> on
> Agilex7M, and update Agilex PLL sync-to-async configuration.
> 
> Gen5 / Arria10 and cleanup
> Improve QTS handoff prepare isolation, fix the PL330 TARGET-to-ARCH naming,
> enable DesignWare watchdog and random MAC on Arria10, and apply related
> Kconfig, FPGA, clock and MAINTAINERS cleanups.

And I did miss that you had the changelog here at the bottom, sorry.
It's helpful but not required to have it in the tag, and most of the
time people put it up top, so I just wasn't expecting it here.

-- 
Tom

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