[RESEND PATCH 0/2] mmc: sdhci-cadence6: fix PHY programming reliability
| Newsgroups | gmane.comp.boot-loaders.u-boot.general,gmane.comp.boot-loaders.u-boot |
|---|---|
| Message-ID | <[email protected]> |
From: Tze Yee Ng <[email protected]> Two standalone fixes for the Cadence SD6HC (v6) PHY programming path in sdhci-cadence6.c. Patch 1 reads back HRS05 after each indirect PHY register write so the posted write is flushed before the next PHY access; without it, back-to-back PHY configuration writes can race and leave the PHY partially programmed. Patch 2 adds a settle delay after the PHY/DLL is reprogrammed and the DLL reset released, so the analog read/write path has relocked before the first data transfer is issued. These were found while bringing up the UHS-I higher-speed modes on Agilex5, but the fixes are not Agilex5-specific. The mode enablement is sent as a separate follow-up series ("mmc: sdhci-cadence6: harden PHY config tables and enable Agilex5 UHS modes") that builds on top of these two fixes. Resending because one of the maintainers was missed in the Cc list on the original posting. No changes to the patches themselves. Tze Yee Ng (2): mmc: sdhci-cadence6: flush posted writes to PHY registers mmc: sdhci-cadence6: wait for the PHY to settle after adjustment drivers/mmc/sdhci-cadence6.c | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) -- 2.43.7