Re: selective drc error supression

Pierce Keating <[email protected]> Sun, 22 Apr 2007 10:36:08 -0700 (PDT)
Newsgroups gmane.comp.cad.electric.bugs
Message-ID <[email protected]>
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Hi Dima,
   
  Thanks for the tip on connecting via the P-Active arc, that seems to work. I'll have to experiment a bit more to see if I can get rid of other errors of this type. There are a lot of overlap and touching errors in the padframe I downloaded from Mosis but I don't think there's anything I can do about that (beyond re-laying out the pads).
   
  Thank very much!
  Pierce
  

[email protected] wrote:
  Hello Pierce,

Try to connect port of P-transistor and Metal1-P
Active contact by
a short P-Active arc.

If nodes are not connected by arc, Electric doesn't
know that you want them to be connected,
and it thinks that you overlapped them accidently.

-Dima
  Hello,
   
  Is there a way to stop designated DRC errors? For example, when a Metal1-P Active connector is placed on a P transistor active region, a DRC error is generated:
   
  DRC error 4 of 7: Spacing (layer P-Active): node Metal-1-P-Active-Con OVERLAPS arc P-Active [rule 2.2]
   
  However I am merely connecting the transistor drain, so I would like to suppress this error. 
   
  Other times like layers might be intended to touch and a DRC error is correctly generated. However, I would often like to selectively suppress these errors as well. Is there a way to do this? 
   
  Thanks very much,
  Pierce
    
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<div>Hi Dima,</div>  <div>&nbsp;</div>  <div>Thanks for the tip on connecting via the P-Active arc, that seems to work. I'll have to experiment a bit more to see if I can get rid of other errors of this type. There are a lot of&nbsp;overlap and touching&nbsp;errors&nbsp;in the padframe I downloaded from Mosis but I don't think there's anything I can do about that (beyond re-laying out the pads).</div>  <div>&nbsp;</div>  <div>Thank very much!</div>  <div>Pierce</div>  <div><BR><BR><B><I>[email protected]</I></B> wrote:</div>  <BLOCKQUOTE class=replbq style="PADDING-LEFT: 5px; MARGIN-LEFT: 5px; BORDER-LEFT: #1010ff 2px solid">Hello Pierce,<BR><BR>Try to connect port of P-transistor and Metal1-P<BR>Active contact by<BR>a short P-Active arc.<BR><BR>If nodes are not connected by arc, Electric doesn't<BR>know that you want them to be connected,<BR>and it thinks that you overlapped them 
 accidently.<BR><BR>-Dima<BR>  <DIV>Hello,</DIV>  <DIV>&nbsp;</DIV>  <DIV>Is there a way
 to stop designated DRC errors? For example, when a Metal1-P Active connector is placed on a P transistor active region, a DRC error is generated:</DIV>  <DIV>&nbsp;</DIV><FONT size=2>  <DIV><STRONG>DRC error 4 of 7: Spacing (layer P-Active): node Metal-1-P-Active-Con OVERLAPS arc P-Active [rule 2.2]</STRONG></DIV>  <DIV>&nbsp;</DIV>  <DIV>However I am merely connecting the transistor drain, so I would like to suppress this error. </DIV>  <DIV>&nbsp;</DIV>  <DIV>Other times like layers might be intended to touch and a DRC error is correctly generated. However, I would&nbsp;often like to selectively suppress these errors as well. Is there a way to do this? </DIV>  <DIV>&nbsp;</DIV>  <DIV>Thanks very much,</DIV>  <DIV>Pierce</DIV></FONT>  <div>  <HR SIZE=1>  Ahhh...imagining that irresistible "new car" smell?<BR>Check out <A
 href="http://us.rd.yahoo.com/evt=48245/*http://autos.yahoo.com/new_cars.html;_ylc=X3oDMTE1YW1jcXJ2BF9TAzk3MTA3MDc2BHNlYwNtYWlsdGFncwRzbGsDbmV3LWNhcnM-">new cars at Yahoo! Autos.</A> _______________________________________________<BR>Bug-gnu-electric mailing list<BR>[email protected]<BR>http://lists.gnu.org/mailman/listinfo/bug-gnu-electric<BR></BLOCKQUOTE><BR><p>&#32;

      <hr size=1>Ahhh...imagining that irresistible "new car" smell?<br> Check out
<a href="http://us.rd.yahoo.com/evt=48245/*http://autos.yahoo.com/new_cars.html;_ylc=X3oDMTE1YW1jcXJ2BF9TAzk3MTA3MDc2BHNlYwNtYWlsdGFncwRzbGsDbmV3LWNhcnM-">new cars at Yahoo! Autos.</a>

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