Re: How to add bus exports in Layout view.

I Fixed the Bus errors, after I looked closer, it wasn't complaining  
about the Bus naming, but the inputs were connected to the wrong  
input of my gates, for example to input A, instead of input B.   
Mentor Graphics has a feature that treats inputs of gates the same so  
it will resolce errors like this when doing LVS.  Is there any  
settings in Electric that will correct for these type of errors?
Also now that i got the wiring corrected, I am down to the following  
error complaining that my parts don't match, and i'm not sure how to  
get it to pass NCC now, any suggestions?

=================================1211=================================
Hierarchical NCC every cell in the design: cell 'ALU_Control{sch}'   
cell 'ALU_Control{lay}'
Comparing: kal:inv{sch} with: kal:inv{lay}
   exports match, topologies match, sizes not checked in 0.0010 seconds.
Comparing: kal:nand2{sch} with: kal:nand2{lay}
   exports match, topologies match, sizes not checked in 0.0010 seconds.
Comparing: kal:nand3{sch} with: kal:nand3{lay}
   exports match, topologies match, sizes not checked in 0.0010 seconds.
Comparing: kal:nand4{sch} with: kal:nand4{lay}
   exports match, topologies match, sizes not checked in 0.0020 seconds.
Comparing: kal:ALU_Control{sch} with: kal:ALU_Control{lay}
Hash Code Partitioning Failed!!!
5 StratCount doing statistics for entire equivalence class tree
                                             Parts           
Wires          Ports
     # mismatched equiv classes                  8               
0              0
     # matched equiv classes                    22              
31              0
     # active equiv classes                      0               
0              1
     # mismatched net objects                    8               
0              0
     # matched net objects                      44              
62              0
     # active net objects                        0               
0             28

     LeafRec size                       #Part_Recs     #Wire_Recs      
#Port_Recs
           1                                    30              
31              0
          14                                     0               
0              1

     max tree depth                              6
took 2 miliseconds

   8 not-matched Part equivalence classes:
     not-matched Part equivalence class 0
       Cell kal:ALU_Control{sch} has 1 mismatched objects
         kal:nand2 nand2@0 in Cell: kal:ALU_Control{sch} b=net@78  
gnd=gnd y=net@4 vdd=vdd a=Op[0]
       Cell kal:ALU_Control{lay} has 0 mismatched objects
     not-matched Part equivalence class 1
       Cell kal:ALU_Control{sch} has 0 mismatched objects
       Cell kal:ALU_Control{lay} has 1 mismatched objects
         kal:nand2 nand2@0 in Cell: kal:ALU_Control{lay} b=net@20  
gnd=gnd y=net@5 vdd=vdd a=Op[0]
     not-matched Part equivalence class 2
       Cell kal:ALU_Control{sch} has 0 mismatched objects
       Cell kal:ALU_Control{lay} has 1 mismatched objects
         kal:nand2 nand2@1 in Cell: kal:ALU_Control{lay} b=Op[1]  
gnd=gnd y=net@0 vdd=vdd a=net@28
     not-matched Part equivalence class 3
       Cell kal:ALU_Control{sch} has 1 mismatched objects
         kal:nand2 nand2@1 in Cell: kal:ALU_Control{sch} b=Op[1]  
gnd=gnd y=net@9 vdd=vdd a=net@82
       Cell kal:ALU_Control{lay} has 0 mismatched objects
     not-matched Part equivalence class 4
       Cell kal:ALU_Control{sch} has 0 mismatched objects
       Cell kal:ALU_Control{lay} has 1 mismatched objects
         kal:nand3 nand3@4 in Cell: kal:ALU_Control{lay} c=net@5  
gnd=gnd vdd=vdd b=net@601 y=G[3] a=net@218
     not-matched Part equivalence class 5
       Cell kal:ALU_Control{sch} has 1 mismatched objects
         kal:nand3 nand3@4 in Cell: kal:ALU_Control{sch} c=net@9  
gnd=gnd vdd=vdd b=net@22 y=G[2] a=net@25
       Cell kal:ALU_Control{lay} has 0 mismatched objects
     not-matched Part equivalence class 6
       Cell kal:ALU_Control{sch} has 1 mismatched objects
         kal:nand3 nand3@5 in Cell: kal:ALU_Control{sch} c=net@4  
gnd=gnd vdd=vdd b=net@525 y=G[3] a=net@21
       Cell kal:ALU_Control{lay} has 0 mismatched objects
     not-matched Part equivalence class 7
       Cell kal:ALU_Control{sch} has 0 mismatched objects
       Cell kal:ALU_Control{lay} has 1 mismatched objects
         kal:nand3 nand3@2 in Cell: kal:ALU_Control{lay} c=net@0  
gnd=gnd vdd=vdd b=net@213 y=G[2] a=net@291
   exports match, topologies mismatch, sizes not checked in 0.0090  
seconds.
Halting NCC after finding first mismatch
Summary for all cells: exports match, topologies mismatch, sizes not  
checked
NCC command completed in: 0.019 seconds.


On Jan 19, 2007, at 6:39 PM, Steven Rubin wrote:

> At 02:29 PM 1/19/2007, you wrote:
>> How do you add bus exports in a layout view so that they will match
>> up with the
>> bus definitions in the schematic when running NCC?
>>
>> here is the results of the summerize exports on a cell for both the
>> schematic and layout views, The cell fails NCC, and I don't know how
>> to label the input ports on the layout so that they match the bus
>> port in the schematic.
>>
>> ----- Exports on cell 'ALU_Control{lay}' -----
>> Input ports 'Op[0,1,2]'
>> Output export 'Cin'
>> Output ports 'G[0,1,2,3,4,5,6,7]'
>>
>> ----- Exports on cell 'ALU_Control{sch}' -----
>> Input export 'Op[2:0]'
>> Output export 'Cin'
>> Output export 'G[0:7]'
>
> This is the correct way to do it.  There are no layout busses, so  
> you just create individual exports that match the bus entry names.
>
> If NCC is failing, then perhaps there is some other problem than  
> export name matching.  You may want to send a small example to me.
>
>    -Steven Rubin
>
>