Can Electric read in VHDL source files

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I am new to the Electric tool. I am curious to know if Electric can read in
a
standard VHDL circuit file, and simulate it, or generate the netlist. Could
someone please provide some pointers in this regard ? thanks in advance
for your help.

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I am new to the Electric tool. I am curious to know if Electric can read in a <br>
standard VHDL circuit file, and simulate it, or generate the netlist. Could<br>
someone please provide some pointers in this regard ? thanks in advance<br>
for your help.<br>
<br><br><br>

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