Re: simulation

At 04:11 AM 3/8/2005, you wrote:
>Hello,
>How can I start a simulation with verilog?
>How can I start a waveform for verilog?
>I try with the example in tool-simulate-verilog but I
>did'nt see any waveform?

When a new simulation begins, the waveform window is sometimes empty.  The 
user must then load signals into it.  This can be done from the "explorer" 
tree on the left side of the waveform window (under the "SIGNALS" entry) or 
by selecting signals in the original circuit and adding them (type "a") to 
the waveform window.  When in doubt, read the manual, which is built into 
Electric, under the "Help" menu.

    -Steven Rubin