Re: VHDL Error in 8.02

At 10:56 PM 7/3/2005, you wrote:
>I have created a schematic that has a 2-bit bus for input and two
>single wires for output. The bus is ripped and the lines are sent
>through two buffers to the output wires. The VHDL is correct and
>this circuit will run through the ALS simulator in Electric 8.02.
>
>I then created an IC for this circuit and placed it in another schematic.
>The new schematic has a 2-bit bus input export and two wire output
>exports. These exports are mapped to the input and output ports of
>the IC.
>
>The call to the IC in the VHDL is incorrect.  The network name is incorrect.
>It reads A_1_0 twice instead of A_1_ and A_0_. The port is not recognized
>as it should, it is labeled as 'open'.
>
>There is no network named A_1_0_ in the cells.
>This seems to be a problem with the VHDL generator.
>I have attached the jelib that has this example in it.
>
>Here is the VHDL that is generated:
>
>-- VHDL automatically generated from cell 'call_split{sch}'
>entity call_split is port(A_1_, A_0_: in BIT; D0, D1: out BIT);
>  end call_split;
>
>architecture call_split_BODY of call_split is
>  component split port(A_1_0_, A_1_0_: in BIT; D0, D1: out BIT);
>    end component;

Thanks for the bug report.  Here is how to fix it (if you are playing with 
the source code):

In the module com.sun.electric.user.GenerateVHDL.java, find the method 
"addPortList()".
In that method, just before the comment "// flag important ports", add this 
line:

         if (ni != null && np instanceof Cell) nl = 
((Cell)np).acquireUserNetlist();

This will generate proper VHDL.

Of course, there are other problems with the ALS simulator, specifically 
that it is forced to mangle arrayed index names (converting "A[0]" to 
"a_0_") because the VHDL compiler doesn't handle the square brackets properly.

I recommend the IRSIM simulator (if you are dealing with MOS 
transistors).  ALS is only good if you are using digital schematics gates 
(AND, OR, INVERTER, etc.)

    -Steven Rubin