DRC error 1.3

Hello,
The technology I use is MOCMOS.

I've been getting an error note in the DRC check that rule no. 1.3 was
violated-
Minimum spacing, different potential. this is despite the fact that the
areas
for which I get the error are the same potential- e.g.- I get it for
different
parts of the same well or for two NMOS transistor connected serially. Do you
know what is the reason for that error and how I can solve it?

Thanks

Oren