FPGAs

So for this term (and I think only this term, which ends in two weeks 
or so) I get to play with FPGAs.

Now, I've been a bit busy, but I managed to get something going which 
looks a bit like

...
// A = S[1] = ROTL3(S[1]+(s_1[31:0]+l_1[31:0]))
	reg [831:0]s_2;
	wire [31:0]rotl3out_2;
	rotl3(s_1[63:32]+s_1[31:0]+l_1[31:0], rotl3out_2);
	always @(posedge CLK) s_2 <= { s_1[831:64], rotl3out_2, s_1[31:0] };
// B = L[1] = ROTL(L[1]+(rotl3out_2+l_1[31:0]),rotl3out_2+l_1[31:0])
	reg [95:0]l_2;
	wire [31:0]rotlout_2;
	rotl(l_1[63:32]+rotl3out_2+l_1[31:0],rotl3out_2+l_1[31:0], rotlout_2);
	always @(posedge CLK) l_2 <= { l_1[95:64], rotlout_2, l_1[31:0] };
...

It's in Verilog, and perhaps VHDL would be better (I don't know). But 
it optimises out all the bits of the s_1 register, and some 200 bits of 
the s_21 register (and it took absolutely ages to copy the list of 
warnings), which makes me think I've done something wrong.

It's also about five times too big to fit on the FPGA, and this is only 
half of the work (was too lazy to code the other half of the loop). I'd 
send the code, but I'm not sure what the large email/attachment rules 
for this list are (if there are any).

One option is to pipeline it less, reducing the number of DFFs required 
(which I suspect is the limiting factor). Another is to ask nicely and 
see if I can get a bigger FPGA (4000 logic elements is tiny!).

I suspect fixing the bugs in my algorithm is quite a high priority 
though.

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