Re: RC5 with FPGAs

Doing a quick survey of the hardware list, there seems to be many people(me
included), that seem, to various stages, to be dabbling with an FPGA (or
other soft silicon) implementation.
I hereby propose that we make a central area for such developments, to
coordinate development.
Another techinical idea: Instead of fine tuning each implementation to each
FPGA, we could have one "main" code, and use a core generator program to
tune it to each individual FPGA, to allow for maximum optimization.


On 9/5/06, Fugu <[email protected]> wrote:
>
> By the way, I am also working on a FPGA implementation.
> A technique that can accelerate keyspeed is this:
> 1) Use pipelining
> 2) Have the maximum numbers of decryption engines, as to use all the
> gates.
> BTW, posting your core on opencores.org would enable it to be checked for
> bugs and improved.
>
>
> On 6/14/06, Jim C. Nasby < [email protected]> wrote:
> >
> > On Wed, Jun 14, 2006 at 03:13:04PM -0600, Fugu wrote:
> > > One could do hardware error detection by re-encrypting the "decrypted"
> > > message by the same key, and comparing it to the given message.
> >
> > Yes, but that gives much less protection than checking things on the
> > server does.
> > --
> > Jim C. Nasby, Database Architect            [email protected]
> > Give your computer some brain candy! www.distributed.net Team #1828
> >
> > Windows: "Where do you want to go today?"
> > Linux: "Where do you want to go tomorrow?"
> > FreeBSD: "Are you guys coming, or what?"
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>
>
>
> --
> FIN|ACK
>



-- 
FIN|ACK

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