Re: RC5 with FPGAs

On Sep 7, 2006, at 5:26 AM, david fleischer wrote:

> That's interesting.
> How does byte-reversed increment work?

In some of my software cores I reversed the order of the bytes in the  
key, increment the byte that came from the most significant byte of  
the original key then reverse the byte order again.

> You suggest doing 6 rounds instead of 3. This to avoid
> the penalty of storing the array until the key is
> tested. But the RC5 algorithm is separated into
> stages. You need all the data for the last step, so
> you need at least to have gone through 2 rounds when
> starting to encrypt the words.
> How does the pyramid work?

I'm most familiar with RC5-64, the numbers may be different for  
RC5-72. The algorithm uses 3 rounds with 26 iterations in each round.  
The output of each iteration produces an Sn(i) that is passed to the  
same iteration of the next round and an L(j) that is passed to the  
subsequent 2 or 3 iterations. Looking at the first iteration of round  
3, we need the inputs of L() produced at the end of round 2 and S2(0)  
produced in the first iteration of round 2. What we do is make 2  
instances of the hardware for round 2 and time the inputs so that  
when round 3 need it's data one instance is providing the L() inputs  
and the other instance is providing the S2() input. Similarly, each  
instance of round 2 needs to be fed from 2 instances of round 1  
(except only 3 instances are needed).

The pyramid looks something like:
.
             R1
             v
       R1 -> R2
       v     v
R1 -> R2 -> R3 -> E

where the horizontal arrows are the S() values being passed and the  
vertical arrows are the L() values being passed. To fully expand this  
for processing 1 key per cycle, each line is replicated 26 times as  
in this sample:

.
                R1.0
                 v
                R1.1
                 v
.
.
.
                 v
                R1.25
                 v
         R1.0 -> R2.0
          v      v
.
.
.
          v      v
         R1.24 -> R2.24
          v      v
         R1.25 -> R2.25 (PT)
          v      v       v
R1.0 -> R2.0 -> R3.0 -> E.0
  v       v       v      v
R1.1 -> R2.1 -> R3.1 -> E.1
  v       v       v      v
.
.
.
  v       v       v      v
R1.25-> R2.25-> R3.25-> E.25
                         v
                        (CT)

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