Re: As everybody get up ...

Hi Guerric,

AWESOME :) .... under 18500 slices, 37K LUT's is a pretty nice fit.
Slightly better than where mine tiled out on the Virtex-E's, before
I gave up with fine tuning the floor planning for PAR so it would
actually route.

I assume done with tiled macros and hand placement to avoid
the routing mess from the pipeline terms between stages?

Can you tell us more? Combinatorial depth per pipeline stage?
Did you break it per stage, or twice per stage (for arithmetics
and the shifters)? What did you use for the retiming memory, LUT
rams or shifters? HDL design? Schematic Design?

Have fun,
John

	Hello,

	As everybody is getting up :), I will try to find the time to finalize
	our RC5 core.

	It is a fully unrolled (and pipelined) core.

	It is quite optimized (I'm a HDL designer) and the target is currently
	Virtex4-LX FPGA (but it don't use much of specific features of this
	platform).

	It should fit in a LX40 device (18500 slices max) (no chance to fit
	into a S3-200 :) ). Frequency should be around 200 Mhz (or more) and 1
	key test per clock cycle.

	I hope to give you good news in a few days.
	Of course, the source will be given as there no commercial interest
	for a high throughput key scheduler (which is the main part of a RC5
	brute force engine).

	PS: still remains the possibility of working on separate ranges,
	dedicated to FPGAs (or others). At least at the beginning, before
	finding a better solution.

	-- 
	Guerric Meurice de Dormale
	UCL DICE/Crypto Group
	http://www.dice.ucl.ac.be/crypto/
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