partially unrolled?
"ABC XYZ" <[email protected]> Wed, 1 Nov 2006 20:02:46 +0100
| Newsgroups | gmane.comp.distributed-net.hardware |
|---|---|
| Message-ID | <[email protected]> |
I read on this list that a fully unrolled design is too large for any FPGAs we can afford, while a fully iterated is probably too slow to be useful. Someone mentioned something about a "partially" unrolled design. Can you guys explain to me how that works? I tried myself to partially unroll RC5-72, but whatever I write has a worse LUT/keys ration that the fully iterated design. Can anyone give me an example of an intelligent partially unrolled design?? regards, ABC _______________________________________________ Hardware mailing list Hardware-Ra3b/QYEcJ3d140v2zMXi0fjHoOT/h/[email protected] http://lists.distributed.net/mailman/listinfo/hardware