Getting close to an FPGA design

Hello,

Ok, I can investigate the partially unrolled solution too.
I plan to do the following:
Use 3 times a pair of key schedule blocs (1 for each key schedule
round). Use 1 encryption bloc. It follows what suggested Dan Oetting.

I think a pair is a good idea since an encrypt bloc takes the output
of 2 key schedule blocs. Moreover, big ShiftRegister using bRAMs have
two inputs/outputs.

I think it is necessary to have a big enough design in order to not
lose all the efficiency in muxes of the loading circuitry.

I'm finishing the fully unrolled circuit.
First rough estimation: 17400 Slices, 26 bRAMs, 230 Mhz on a XCV4LX40-10
I have 5 pipeline stages per KeySchedule blocs and 10 per Encrypt
blocs.

Of course, it is still possible to spend more bRAMs to save hundreds
of slices (but it probably doesn't worth it).

A partially unrolled design (as explained above) should take very
roughly 1750 slices and 2 bRAMs.

PS: bRAMS are used for storage of S[].
PS2: I can't see how to avoid storage of S[] in my case. Whatever,
those bRAMs are fine for that purpose.

-- 
Guerric


_______________________________________________
Hardware mailing list
Hardware-Ra3b/QYEcJ3d140v2zMXi0fjHoOT/h/[email protected]
http://lists.distributed.net/mailman/listinfo/hardware