Re: Fully unrolled RC5 on FPGA

Hello,

I think the best thing to do is to wait for partially unrolled results.
This could make possible the use of cheaper FPGA. 
The aim is of course to look at the performances/cost ratio: the fully
unrolled is the most efficient but maybe a less efficient one can fit
on a cheap fpga. In particular, I would like to look at a 1/13
unrolled design (6 Keyschedule module + 1 encrypt module) and a half
fully unrolled design

Probably building boards with cheap spartan3E can lead to an efficient
solution. I think a fully unrolled design is a good point of
comparison, but maybe not the best choice.

A previous work about building clusters of FPGA is available here.
http://www.crypto.ruhr-uni-bochum.de/imperia/md/content/texte/publications/conferences/ches2006_copa.pdf

Their solution is interesting but there is two issues:
- They have power problem (to feed all the fpga through the "lane" (or
wire, not sure of the word) of the PCB)
- I think FPGAs are too close in the cluster. As a result, heat
dissipation is not really good and the clock frequency have to be
lowered (they should probably add dissipators and/or fans)

For a homemade board, it is probably better to limit the extra
features in order to limit the cost. If many features are required, it
is probably better to buy a board already available (to limit the risk
and development costs). If the board is too generic, it is required to
provide support softwares for communications, and why not reference
designs, ... (probably not our job).

So what's the best solution?
- building its own small board
- building a kind of cluster (copacobana-like)
- to buy boards from company (I can't find LX40 boards :( )

By the way, a rate of (theoretically) 480Mbps for the USB 2.0 is not
fast enough for general purpose applications ?

PS: I currently can provide the .bit file for devices not available
with the webpack.

-- 
Guerric


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