Re: The market of ASICs (One GigaKey / Second?)

On Mon, Jul 12, 2004 at 06:58:39AM +0200, Michael Meeuwisse wrote:
> The RC5 algorithm is quite easy to translate to a pipeline, which, as every 
> other pipeline on the planet, can push out a key check every clock cycle. 
> With today's technologies (i hope) i'm not underestimating things when i 
> say that one Gigakey every second (that's not a typo, that's what... 
> 1.5block every second? ) is possible.
> 
> But then there's something called math. (Technical stuff lower, skip if not 
> interested)
> 
> The expanded key table is S[T-1] long, T depends on R (2*(R+1) to be 
> exact), R is usually 12. That makes S quite big. And because we wanted this 
> in a pipeline (my estimations: about 600 stages) it sums up at S[25..0] + 
> say... 4 extra vars (think L, think current key), times 32 bits, times 600 
> stages, divided by 8 for bytes, that makes 72KiB. Not that much, right?
> Then there is bandwith to that small amount of memory. Every stage we need 
> to read and write a lot to this. I'm not going to lay it out to you (and 
> some people might want to argue this number: feel free) but my calculations 
> resulted in numbers around 240 Gigabyte every second. And that's DDR'ed. 
> And no, don't think that bursting numbers will get it much lower. And don't 
> even start about managing this amount of bandwith required. Fact: it's 
> impossible for external memory, internal memory (in FPGA's, or other candy) 
> isn't even an argument.

If you're pipelining, why do you need memory for any of the intermediate
stuff?
-- 
Jim C. Nasby, Database Consultant                  [email protected]
Member: Triangle Fraternity, Sports Car Club of America
Give your computer some brain candy! www.distributed.net Team #1828

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