Re: Fully unrolled RC5 on FPGA

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If we will use a microcontroller to control the FPGA, an AVR would be much
better than a PIC for many reasons:
*more register space
*a GCC port
*higher speed.

Notice that we got to the FPGA before Folding at Home!

On 11/15/06, [email protected] <[email protected]> wrote:
>
> Bonjour,
>
> Tuesday, November 14, 2006, 8:41:25 PM, you wrote:
>
> JLB> Hi Guerric,
>
> JLB> Any chance I can get you go target your design to an XCV2000E-6BG560C
> JLB> and tell me if it fits and what the clock rate estimate is?
>
> JLB> It's just a data point for me to compare two year old data to the
> XCV4LX
> JLB> numbers.
>
> JLB> Thanks,
> JLB> John
>
> Ok, I can do that.
> The design will need 4 times the number of bRAMs compared with the
> Virtex4 design: 16-bit data width and no "read before write" mode.
>
> With this kind of RAMs, a register on the B signal of the KeySchedule
> bloc could be saved using the fact that input is mirrored to the
> output of the bRAM while writing. I currently don't plan to make this
> optimization. (this would mean a saving of 26*3 *32/2 = 1250 Slices).
> Whatever, it is probably bad from a place&route point of view.
>
> I will test the full design with the new long shift register and will
> provides the implementation results.
>
> --
> Guerric
>
>
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-- 
-----------------------
Olivier V. Meyer
Congress shall make no law respecting an establishment of religion, or
prohibiting the free exercise thereof; or abridging the freedom of speech,
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petition the government for a redress of grievances.

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If we will use a microcontroller to control the FPGA, an AVR would be much better than a PIC for many reasons:<br>*more register space<br>*a GCC port<br>*higher speed.<br><br>Notice that we got to the FPGA before Folding at Home!
<br><br><div><span class="gmail_quote">On 11/15/06, <b class="gmail_sendername"><a href="mailto:[email protected]">[email protected]</a></b> &lt;<a href="mailto:[email protected]">[email protected]
</a>&gt; wrote:</span><blockquote class="gmail_quote" style="border-left: 1px solid rgb(204, 204, 204); margin: 0pt 0pt 0pt 0.8ex; padding-left: 1ex;">Bonjour,<br><br>Tuesday, November 14, 2006, 8:41:25 PM, you wrote:<br>
<br>JLB&gt; Hi Guerric,<br><br>JLB&gt; Any chance I can get you go target your design to an XCV2000E-6BG560C<br>JLB&gt; and tell me if it fits and what the clock rate estimate is?<br><br>JLB&gt; It's just a data point for me to compare two year old data to the XCV4LX
<br>JLB&gt; numbers.<br><br>JLB&gt; Thanks,<br>JLB&gt; John<br><br>Ok, I can do that.<br>The design will need 4 times the number of bRAMs compared with the<br>Virtex4 design: 16-bit data width and no &quot;read before write&quot; mode.
<br><br>With this kind of RAMs, a register on the B signal of the KeySchedule<br>bloc could be saved using the fact that input is mirrored to the<br>output of the bRAM while writing. I currently don't plan to make this<br>
optimization. (this would mean a saving of 26*3 *32/2 = 1250 Slices).<br>Whatever, it is probably bad from a place&amp;route point of view.<br><br>I will test the full design with the new long shift register and will<br>provides the implementation results.
<br><br>--<br>Guerric<br><br><br>_______________________________________________<br>Hardware mailing list<br><a href="mailto:Hardware-Ra3b/QYEcJ3d140v2zMXi0fjHoOT/h/[email protected]">Hardware-Ra3b/QYEcJ3d140v2zMXi0fjHoOT/h/[email protected]</a><br><a href="http://lists.distributed.net/mailman/listinfo/hardware">
http://lists.distributed.net/mailman/listinfo/hardware</a><br></blockquote></div><br><br clear="all"><br>-- <br>-----------------------<br>Olivier V. Meyer<br>Congress shall make no law respecting an establishment of religion, or prohibiting the free exercise thereof; or abridging the freedom of speech, or of the press; or the right of the people peaceably to assemble, and to petition the government for a redress of grievances.

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