Fully unrolled RC5 core, pipelined and retimed using LUT RAMs
"John L. Bass" <jbass-/[email protected]> Sun, 26 Nov 2006 07:47:27 -0700
| Newsgroups | gmane.comp.distributed-net.hardware |
|---|---|
| Message-ID | <[email protected]> |
Hi Guys,
Went digging thru my archives and backup tapes till I found the core generator
below. It produces a correctly retimed fully unrolled pipelined RC5 engine targeted
for C (actually ment as an example for FpgaC project someday). It's easily converted
to Verilog, with some very minor changes to the generator's production printf's.
Included is a C test bench to verify correct operation of the core, using
the following build process, and produce the single line result below:
cc rc5-72gen.c -o rc5-72gen
./rc5-72gen > rc5-72core.h; rm -f rc5-72gen
cc rc5-72tb.c -o rc5-72tb
./rc5-72tb; rm -f rc5-72tb
Core IS correct, latency=180
The latency is reported as 180 clocks because the initial Key has 100
substracted from the correct result, adding 100 cycles before the correct
key is presented to the core.
The files 72CheckEterms.h and 72CheckSBox.h can be included just before
the closing brace in the rc5-72core.h file for debugging if you break
the pipelining with changes. They are commented out in the example below.
This core has an 80 cycle latency, and is moderately optimal in a space/time
sense. The fanout for the Sctr and Lctr is huge, and needs some reasonable
care ... in addition, you should probably make it a Grey Code for a small
power savings. Because it pipelines a full stage, it's combinatorial depth
is pretty deep, and will probably not come near device speed on most FPGA
architectures. I've done a LOT better using hand optimized hard macros and
other partitioning strategies, starting with stages here and hand optimizing
using the FPGA editor.
I offer the generator and test bench below as a starting point for anyone
else that's interested in pipelined fully unrolled FPGA RC5 engines. Pipelining
designs like this is non-trival, and requires some serious thought on retiming.
For a newbie, this is a bit of a challenge the first time, so hopefully this
example will be a useful learning tool. The arrays SRxx[26] and LRxx[3] below
are 26 stage and 3 stage retiming fifo's. In addition you will find ERxx terms
which are one state FF's for retiming as well. While this design is based
on using LUT RAM's, other choices, like using BRAMs are possible.
For FpgaC, pipelining is done by reversing the order of the stages in the
pipeline, to force implicit parallelism by removing the sequential dependency
flow that would normally produce a very deep combinatorial chain. Thus every
stage in the core is fully parallel on an FPGA or other massively parallel
MIMD architecture. This is fully testable in a sequential processor since
the prior stages/clocks results are held in local variables between loops on
the core, and referenced before being updated again.
Have fun!
John
--------------------------- rc5-72gen.c ---------------------------------------
/*
* Construct unrolled pipelined RC5 key check engine
* This may freely be used, as long as copyright notices are maintained per BSD licensing
* John L. Bass, Copyright 2003
*/
main( )
{
const unsigned int P = 0xB7E15163;
const unsigned int Q = 0x9E3779B9;
static unsigned int S[26] = {0, 0};
int e, i, s, l;
printf("/* John L. Bass, Copyright 2003 */\n\t{\n");
printf("\t\tstatic int Lctr, Sctr;\n");
printf("\n");
for (s=0;s<(3*26);s++) {
if((s%10) == 0) printf("\t\tunsigned long ");
printf("S%02d",s);
if((s%10) < 9 && s != 77) printf(", ");
else printf(";\n");
}
printf("\n");
for (s=0;s<(3*26+2);s++) {
if((s%10) == 0) printf("\t\tunsigned long ");
printf("L%02d",s);
if((s%10) < 9 && s != 79) printf(", ");
else printf(";\n");
}
printf("\n");
for (e=0;e<(1*26+3);e++) {
if((e%10) == 0) printf("\t\tunsigned long ");
printf("E%02d",e);
if((e%10) < 9 && e != 28) printf(", ");
else printf(";\n");
}
printf("\n");
for (s=0;s<(2*26);s++) {
if((s%10) == 0) printf("\t\tunsigned long ");
printf("SR%02d[26]",s);
if((s%10) < 9 && s != 51) printf(", ");
else printf(";\n");
}
printf("\n\t\tunsigned long ER01, ");
for (s=2;s<(1*26+2);s++) {
if((s%10) == 0) printf("\t\tunsigned long ");
printf("ER%02d",s);
if((s%10) < 9 && s != 27) printf(", ");
else printf(";\n");
}
printf("\n\t\tunsigned long LR01, ");
for (s=2;s<(3*26+2);s++) {
if((s%10) == 0) printf("\t\tunsigned long ");
printf("LR%02d[3]",s);
if((s%10) < 9 && s != 79) printf(", ");
else printf(";\n");
}
/* round 0 - Key Expansion Prep, Random Field */
if(S[0] == 0) {
S[0]= P;
for (s=1;s<26;s++)
S[s]= S[s-1] + Q;
}
printf("\n");
printf("\t\t// Pipeline Stage %2d, completion ----------------\n", 79);
e--;
printf("\t\tE%02d = E%02d ^ Cipher(1);\n",e,--e-2);
printf("\t\tE%02d = ER%02d ^ Cipher(0);\n",e,--e-2);
printf("\t\tMiss = E%02d & E%02d;\n",e,e+1);
printf("\n");
/* rounds 3 - Key Expansion*/
for (s=77,l=80;s>=(2*26);s--,l--)
{
printf("\t\t// Pipeline Stage %2d, round 3 -------------------\n", s+1);
printf("\t\tS%02d = Rotl3(SR%02d[Sctr] + S%02d + L%02d);\n", s,s-26,s-1,l-1);
if(s != 77)
printf("\t\tL%02d = Rotl(LR%02d[Lctr] + S%02d + L%02d, S%02d + L%02d);\n", l,l-3,s,l-1,s,l-1);
if(s != 77)
printf("\t\tLR%02d[Lctr] = L%02d;\n", l,l);
if(s == 53) {
printf("\t\tE%02d = Plain(1) + S%02d;\n",1,s);
printf("\t\tE%02d = Plain(0) + S%02d;\n",e=0,s-1);
}
if(s == 54) {
printf("\t\tE%02d = Rotl(E%02d ^ E%02d, E%02d) + S%02d;\n",e, e-2,e-1,--e-1,s);
printf("\t\tER%02d = E%02d;\n",e-1, e-1);
}
if(s > 54) {
printf("\t\tE%02d = Rotl(ER%02d ^ E%02d, E%02d) + S%02d;\n",e, e-2,e-1,--e-1,s);
printf("\t\tER%02d = E%02d;\n",e-1, e-1);
}
}
printf("\n");
/* rounds 2 - Key Expansion*/
for (;s>=(1*26);s--,l--)
{
printf("\t\t// Pipeline Stage %2d, round 2 -------------------\n", s+1);
printf("\t\tS%02d = Rotl3(SR%02d[Sctr] + S%02d + L%02d);\n", s,s-26,s-1,l-1);
printf("\t\tSR%02d[Sctr] = S%02d;\n", s,s);
printf("\t\tL%02d = Rotl(LR%02d[Lctr] + S%02d + L%02d, S%02d + L%02d);\n", l,l-3,s,l-1,s,l-1);
printf("\t\tLR%02d[Lctr] = L%02d;\n", l,l);
}
printf("\n");
/* round 1 - Key Expansion */
for (;s>1;s--,l--)
{
printf("\t\t// Pipeline Stage %2d, round 1 -------------------\n", s+1);
printf("\t\tS%02d = Rotl3(0x%08x + S%02d + L%02d);\n", s,S[s],s-1,l-1);
printf("\t\tSR%02d[Sctr] = S%02d;\n", s,s);
printf("\t\tL%02d = Rotl(LR%02d[Lctr] + S%02d + L%02d, S%02d + L%02d);\n", l,l-3,s,l-1,s,l-1);
printf("\t\tLR%02d[Lctr] = L%02d;\n", l,l);
}
printf("\n");
printf("\t\t// Pipeline Stage %2d, round 1 -------------------\n", s+1);
printf("\t\tS%02d = Rotl3(0x%08x + S%02d + L%02d);\n", s,S[s],s-1,l-1);
printf("\t\tSR%02d[Sctr] = S%02d;\n", s,s);
printf("\t\tL%02d = Rotl(LR%02d + S%02d + L%02d, S%02d + L%02d);\n", l,l-3,s,l-1,s,l-1);
printf("\t\tLR%02d[Lctr] = L%02d;\n", l,l); l--;
printf("\n");
printf("\t\t// Pipeline Stage %2d, round 1 -------------------\n", s);
printf("\t\tS%02d = Rotl3(0x%08x);\n", 0,S[0]);
printf("\t\tSR%02d[Sctr] = S%02d;\n", 0,0);
printf("\t\tL%02d = Rotl(L%02d + S%02d, S%02d);\n", l,0,0,0);
printf("\t\tLR%02d[Lctr] = L%02d;\n", l,l);l--;
printf("\t\tLR01 = L01;\n");
printf("\n");
printf("\t\t// Pipeline Stage %2d, round 1 -------------------\n", 0);
printf("\t\tL02 = Key(2);\n",l,l);
printf("\t\tLR%02d[Lctr] = L%02d;\n", l,l);l--;
printf("\t\tL01 = Key(1);\n",l,l); l--;
printf("\t\tL00 = Key(0);\n",l,l);
printf("\t\tSctr = ++Sctr % 26;\n");
printf("\t\tLctr = ++Lctr % 3;\n");
printf("\t}\n");
exit(0);
}
--------------------------- 72CheckEterms.h ---------------------------------------
/*
* Validate RSA-72 E term data flow in unrolled pipelined RC5 key check engine
* This may freely be used, as long as copyright notices are maintained per BSD licensing
* John L. Bass, Copyright 2003
*/
{
static int Phase;
if(E00 == 0x30566d91) printf("E00 == 0x30566d91 at %d\n", Phase);
if(E01 == 0x14dec230) printf("E01 == 0x14dec230 at %d\n", Phase);
if(E02 == 0x52ab72d8) printf("E02 == 0x52ab72d8 at %d\n", Phase);
if(E03 == 0x39322dc9) printf("E03 == 0x39322dc9 at %d\n", Phase);
if(E04 == 0x75f45bdb) printf("E04 == 0x75f45bdb at %d\n", Phase);
if(E05 == 0xff8b6414) printf("E05 == 0xff8b6414 at %d\n", Phase);
if(E06 == 0x48c95506) printf("E06 == 0x48c95506 at %d\n", Phase);
if(E07 == 0x5ef5d545) printf("E07 == 0x5ef5d545 at %d\n", Phase);
if(E08 == 0x29059d53) printf("E08 == 0x29059d53 at %d\n", Phase);
if(E09 == 0xd507c863) printf("E09 == 0xd507c863 at %d\n", Phase);
if(E10 == 0xc5a8e903) printf("E10 == 0xc5a8e903 at %d\n", Phase);
if(E11 == 0x35c71266) printf("E11 == 0x35c71266 at %d\n", Phase);
if(E12 == 0x97b22b29) printf("E12 == 0x97b22b29 at %d\n", Phase);
if(E13 == 0x06927975) printf("E13 == 0x06927975 at %d\n", Phase);
if(E14 == 0xb28efb3d) printf("E14 == 0xb28efb3d at %d\n", Phase);
if(E15 == 0x1fbae731) printf("E15 == 0x1fbae731 at %d\n", Phase);
if(E16 == 0xb779a1fe) printf("E16 == 0xb779a1fe at %d\n", Phase);
if(E17 == 0x329a7ae7) printf("E17 == 0x329a7ae7 at %d\n", Phase);
if(E18 == 0xed95b286) printf("E18 == 0xed95b286 at %d\n", Phase);
if(E19 == 0x84a87873) printf("E19 == 0x84a87873 at %d\n", Phase);
if(E20 == 0x9842751f) printf("E20 == 0x9842751f at %d\n", Phase);
if(E21 == 0xfe22f21f) printf("E21 == 0xfe22f21f at %d\n", Phase);
if(E22 == 0xff96025b) printf("E22 == 0xff96025b at %d\n", Phase);
if(E23 == 0x19d89e11) printf("E23 == 0x19d89e11 at %d\n", Phase);
if(E24 == 0x562d285a) printf("E24 == 0x562d285a at %d\n", Phase);
if(E25 == 0x2fb7852a) printf("E25 == 0x2fb7852a at %d\n", Phase);
Phase++;
}
--------------------------- 72CheckSBox.h ---------------------------------------
/*
* Validate RSA-72 SBox data flow in unrolled pipelined RC5 key check engine
* This may freely be used, as long as copyright notices are maintained per BSD licensing
* John L. Bass, Copyright 2003
*/
{
static int Phase;
if(S01 == 0xbb2849ae) printf("S01 == 0xbb2849ae at %d\n", Phase);
if(S02 == 0xf5f1c3a6) printf("S02 == 0xf5f1c3a6 at %d\n", Phase);
if(S03 == 0xb460ef5c) printf("S03 == 0xb460ef5c at %d\n", Phase);
if(S04 == 0xace26a66) printf("S04 == 0xace26a66 at %d\n", Phase);
if(S05 == 0xc6cc15c4) printf("S05 == 0xc6cc15c4 at %d\n", Phase);
if(S06 == 0x3bb5ca11) printf("S06 == 0x3bb5ca11 at %d\n", Phase);
if(S07 == 0x371ad8e1) printf("S07 == 0x371ad8e1 at %d\n", Phase);
if(S08 == 0x8c3c25b8) printf("S08 == 0x8c3c25b8 at %d\n", Phase);
if(S09 == 0xc2907f0a) printf("S09 == 0xc2907f0a at %d\n", Phase);
if(S10 == 0x3485279c) printf("S10 == 0x3485279c at %d\n", Phase);
if(S11 == 0x0c8239a8) printf("S11 == 0x0c8239a8 at %d\n", Phase);
if(S12 == 0x3f76341c) printf("S12 == 0x3f76341c at %d\n", Phase);
if(S13 == 0xdfb742d2) printf("S13 == 0xdfb742d2 at %d\n", Phase);
if(S14 == 0x5d5e3ebc) printf("S14 == 0x5d5e3ebc at %d\n", Phase);
if(S15 == 0xeed01812) printf("S15 == 0xeed01812 at %d\n", Phase);
if(S16 == 0xed396354) printf("S16 == 0xed396354 at %d\n", Phase);
if(S17 == 0x0b2a7165) printf("S17 == 0x0b2a7165 at %d\n", Phase);
if(S18 == 0x816b2053) printf("S18 == 0x816b2053 at %d\n", Phase);
if(S19 == 0x395c5c9e) printf("S19 == 0x395c5c9e at %d\n", Phase);
if(S20 == 0x8a61130e) printf("S20 == 0x8a61130e at %d\n", Phase);
if(S21 == 0x39e5a7d1) printf("S21 == 0x39e5a7d1 at %d\n", Phase);
if(S22 == 0x61ab6ce0) printf("S22 == 0x61ab6ce0 at %d\n", Phase);
if(S23 == 0x661118df) printf("S23 == 0x661118df at %d\n", Phase);
if(S24 == 0x40945be3) printf("S24 == 0x40945be3 at %d\n", Phase);
if(S25 == 0x8a16c9ea) printf("S25 == 0x8a16c9ea at %d\n", Phase);
if(S26 == 0x895305ce) printf("S26 == 0x895305ce at %d\n", Phase);
if(S27 == 0x5620c6f6) printf("S27 == 0x5620c6f6 at %d\n", Phase);
if(S28 == 0x56a2b3ac) printf("S28 == 0x56a2b3ac at %d\n", Phase);
if(S29 == 0xc5a84f5d) printf("S29 == 0xc5a84f5d at %d\n", Phase);
if(S30 == 0x6169cb2b) printf("S30 == 0x6169cb2b at %d\n", Phase);
if(S31 == 0x5855a147) printf("S31 == 0x5855a147 at %d\n", Phase);
if(S32 == 0xe73a35da) printf("S32 == 0xe73a35da at %d\n", Phase);
if(S33 == 0x9c6106b0) printf("S33 == 0x9c6106b0 at %d\n", Phase);
if(S34 == 0x7fea785c) printf("S34 == 0x7fea785c at %d\n", Phase);
if(S35 == 0xd47194bc) printf("S35 == 0xd47194bc at %d\n", Phase);
if(S36 == 0x29be047c) printf("S36 == 0x29be047c at %d\n", Phase);
if(S37 == 0x878548ec) printf("S37 == 0x878548ec at %d\n", Phase);
if(S38 == 0x80cafe78) printf("S38 == 0x80cafe78 at %d\n", Phase);
if(S39 == 0x1cb9a02c) printf("S39 == 0x1cb9a02c at %d\n", Phase);
if(S40 == 0xccb679ad) printf("S40 == 0xccb679ad at %d\n", Phase);
if(S41 == 0x06def796) printf("S41 == 0x06def796 at %d\n", Phase);
if(S42 == 0x343b1a44) printf("S42 == 0x343b1a44 at %d\n", Phase);
if(S43 == 0xc04ebb2a) printf("S43 == 0xc04ebb2a at %d\n", Phase);
if(S44 == 0x9e770fa6) printf("S44 == 0x9e770fa6 at %d\n", Phase);
if(S45 == 0x8196809a) printf("S45 == 0x8196809a at %d\n", Phase);
if(S46 == 0x02beee6a) printf("S46 == 0x02beee6a at %d\n", Phase);
if(S47 == 0xe13fd6aa) printf("S47 == 0xe13fd6aa at %d\n", Phase);
if(S48 == 0xa8a9a60e) printf("S48 == 0xa8a9a60e at %d\n", Phase);
if(S49 == 0xa9b761d7) printf("S49 == 0xa9b761d7 at %d\n", Phase);
if(S50 == 0x2dd7cd27) printf("S50 == 0x2dd7cd27 at %d\n", Phase);
if(S51 == 0x64006f95) printf("S51 == 0x64006f95 at %d\n", Phase);
if(S52 == 0xf119c73e) printf("S52 == 0xf119c73e at %d\n", Phase);
if(S53 == 0xe4ed473d) printf("S53 == 0xe4ed473d at %d\n", Phase);
if(S54 == 0xa30a4e50) printf("S54 == 0xa30a4e50 at %d\n", Phase);
if(S55 == 0x50ebb819) printf("S55 == 0x50ebb819 at %d\n", Phase);
if(S56 == 0x43363904) printf("S56 == 0x43363904 at %d\n", Phase);
if(S57 == 0x6d253064) printf("S57 == 0x6d253064 at %d\n", Phase);
if(S58 == 0x4bd0ad13) printf("S58 == 0x4bd0ad13 at %d\n", Phase);
if(S59 == 0x8e699098) printf("S59 == 0x8e699098 at %d\n", Phase);
if(S60 == 0x617594f1) printf("S60 == 0x617594f1 at %d\n", Phase);
if(S61 == 0x945408e1) printf("S61 == 0x945408e1 at %d\n", Phase);
if(S62 == 0xe5963f7c) printf("S62 == 0xe5963f7c at %d\n", Phase);
if(S63 == 0xb04e0766) printf("S63 == 0xb04e0766 at %d\n", Phase);
if(S64 == 0x7bb351ad) printf("S64 == 0x7bb351ad at %d\n", Phase);
if(S65 == 0x1c1fda31) printf("S65 == 0x1c1fda31 at %d\n", Phase);
if(S66 == 0x66fcd733) printf("S66 == 0x66fcd733 at %d\n", Phase);
if(S67 == 0x093756e8) printf("S67 == 0x093756e8 at %d\n", Phase);
if(S68 == 0x7f604796) printf("S68 == 0x7f604796 at %d\n", Phase);
if(S69 == 0x4869a934) printf("S69 == 0x4869a934 at %d\n", Phase);
if(S70 == 0xfba825c4) printf("S70 == 0xfba825c4 at %d\n", Phase);
if(S71 == 0xc0b65ffc) printf("S71 == 0xc0b65ffc at %d\n", Phase);
if(S72 == 0x40972b31) printf("S72 == 0x40972b31 at %d\n", Phase);
if(S73 == 0xefadeb69) printf("S73 == 0xefadeb69 at %d\n", Phase);
if(S74 == 0xcc65bedb) printf("S74 == 0xcc65bedb at %d\n", Phase);
if(S75 == 0xf9caf68f) printf("S75 == 0xf9caf68f at %d\n", Phase);
if(S76 == 0x1d975bbd) printf("S76 == 0x1d975bbd at %d\n", Phase);
if(S77 == 0x0277ae51) printf("S77 == 0x0277ae51 at %d\n", Phase);
Phase++;
}
--------------------------- rc5-72tb.c ---------------------------------------
/*
* Testbench for RC5-72 core
* This may freely be used, as long as copyright notices are maintained per BSD licensing
* John L. Bass, Copyright 2001
*
* included RC5 contest test data included directly from RSA web site for reference.
*/
#define Test72
#define RB(x) \
(((x) >> 24) | (((x) >> 8) & 0x0000FF00) | \
(((x) << 8) & 0x00FF0000) | ((x) << 24))
#ifdef Test72
/*
* Contest identifier: RC5-32/12/9-test
* Cipher: RC5-32/12/9 (RC5 with 32-bit wordsize, 12 rounds, and 9*8=72-bit key)
* State of contest: practice
* Key: c9 0c 03 53 c0 d4 e1 fe 85
* IV: 07 ce 59 1f 86 14 9a 41
* ASCII text: "The RC5-32/12/9-test contest's plaintext"
* Header and message text: "The unknown message is: The RC5-32/12/9-test contest's plaintext"
* Hexadecimal plaintext (after padding):
* 54 68 65 20 75 6e 6b 6e 6f 77 6e 20 6d 65 73 73
* 61 67 65 20 69 73 3a 20 54 68 65 20 52 43 35 2d
* 33 32 2f 31 32 2f 39 2d 74 65 73 74 20 63 6f 6e
* 74 65 73 74 27 73 20 70 6c 61 69 6e 74 65 78 74
* 08 08 08 08 08 08 08 08
*
* Ciphertext:
* 5a 28 2d 56 2a 85 b7 2f ef ae 30 ba 93 54 da 15
* ac ba 79 1a a1 cb 0e 85 9a c3 31 a5 36 19 85 e3
* 77 df dd 07 34 3b fa ed 84 84 41 90 9d 7b 6f 17
* 2d 51 ea b2 1c 5e 45 1c e9 6a 34 de a5 f5 b9 56
* 22 16 e2 60 15 e1 7e b2
*/
unsigned long iv[2] = { RB(0x07ce591f), RB(0x86149a41) };
unsigned long plain[2] = { RB(0x54686520), RB(0x756e6b6e) };
unsigned long cipher[2] = { RB(0x5a282d56), RB(0x2a85b72f) };
unsigned long key[3] = { RB(0xc90c0353), RB(0xc0d4e1fe), RB(0x85000000) };
#endif
#ifdef Test80
/*
* Contest identifier: RC5-32/12/10-test
* Cipher: RC5-32/12/10 (RC5 with 32-bit wordsize, 12 rounds, and 10*8=80-bit key)
* State of contest: practice
* Key: a4 ac 9b af ac b1 27 5f b9 6f
* IV: 31 ef 08 46 e1 43 dd a7
* ASCII text: "The RC5-32/12/10-test contest's plaintext"
* Header and message text: "The unknown message is: The RC5-32/12/10-test contest's plaintext"
* Hexadecimal plaintext (after padding):
* 54 68 65 20 75 6e 6b 6e 6f 77 6e 20 6d 65 73 73
* 61 67 65 20 69 73 3a 20 54 68 65 20 52 43 35 2d
* 33 32 2f 31 32 2f 31 30 2d 74 65 73 74 20 63 6f
* 6e 74 65 73 74 27 73 20 70 6c 61 69 6e 74 65 78
* 74 07 07 07 07 07 07 07
*
* Ciphertext:
* 4d f8 76 d7 e6 49 1a c7 d6 05 e9 37 b5 c2 13 b9
* 29 6f 6c c1 20 18 57 97 6a 37 f1 96 63 b0 7a 7d
* 4f 69 96 97 9a a9 6d 62 2e d2 ca 83 07 74 43 fc
* be 23 4e 6d cf 2f 93 06 a3 26 67 aa 61 0c d8 1d
* 60 ca e8 f5 b1 d9 74 49
*/
unsigned long iv[2] = { RB(0x31ef0846), RB(0xe143dda7) };
unsigned long plain[2] = { RB(0x54686520), RB(0x756e6b6e) };
unsigned long cipher[2] = { RB(0x4df876d7), RB(0xe6491ac7) };
unsigned long key[3] = { RB(0xa4ac9baf), RB(0xacb1275f), RB(0xb96f0000) };
#endif
#ifdef Test88
/*
* Contest identifier: RC5-32/12/11-test
* Cipher: RC5-32/12/11 (RC5 with 32-bit wordsize, 12 rounds, and 11*8=88-bit key)
* State of contest: practice
* Key: 65 82 8d e0 89 1d 6a 88 be c9 cd
* IV: 09 fb 2f 69 87 b2 f2 fd
* ASCII text: "The RC5-32/12/11-test contest's plaintext"
* Header and message text: "The unknown message is: The RC5-32/12/11-test contest's plaintext"
* Hexadecimal plaintext (after padding):
* 54 68 65 20 75 6e 6b 6e 6f 77 6e 20 6d 65 73 73
* 61 67 65 20 69 73 3a 20 54 68 65 20 52 43 35 2d
* 33 32 2f 31 32 2f 31 31 2d 74 65 73 74 20 63 6f
* 6e 74 65 73 74 27 73 20 70 6c 61 69 6e 74 65 78
* 74 07 07 07 07 07 07 07
*
* Ciphertext:
* 76 85 6d dd 78 66 9a 9a a2 57 b5 3c f9 65 7a 44
* 2a 2c f4 8b 8e d8 7a 68 36 c2 cb 6f ed 11 65 01
* d9 3e 3a cc db 29 aa d2 82 5a a1 9a 9b b4 df 79
* e5 a1 35 d7 d5 62 3e 59 4e b8 b1 1e 56 e0 fd a0
* 1a 0a d6 c5 1f 6c dc 62
*/
unsigned long iv[2] = { RB(0x09fb2f69), RB(0x87b2f2fd) };
unsigned long plain[2] = { RB(0x54686520), RB(0x756e6b6e) };
unsigned long cipher[2] = { RB(0x76856ddd), RB(0x78669a9a) };
unsigned long key[3] = { RB(0x65828de0), RB(0x891d6a88), RB(0xbec9cd00) };
#endif
#ifdef Test96
/*
* Contest identifier: RC5-32/12/12-test
* Cipher: RC5-32/12/12 (RC5 with 32-bit wordsize, 12 rounds, and 12*8=96-bit key)
* State of contest: practice
* Key: 67 40 23 1b 6d 1a 7e 0c 92 96 05 c2
* IV: f0 ed e8 46 43 48 bd 62
* ASCII text: "The RC5-32/12/12-test contest's plaintext"
* Header and message text: "The unknown message is: The RC5-32/12/12-test contest's plaintext"
* Hexadecimal plaintext (after padding):
* 54 68 65 20 75 6e 6b 6e 6f 77 6e 20 6d 65 73 73
* 61 67 65 20 69 73 3a 20 54 68 65 20 52 43 35 2d
* 33 32 2f 31 32 2f 31 32 2d 74 65 73 74 20 63 6f
* 6e 74 65 73 74 27 73 20 70 6c 61 69 6e 74 65 78
* 74 07 07 07 07 07 07 07
*
* Ciphertext:
* ae 0e e8 11 df fd c8 d2 06 e9 2e b4 da 75 04 fc
* 33 17 47 91 98 50 0f f5 2e 70 5b f7 38 8b 24 53
* 34 86 40 95 44 46 d5 0a 67 1a 2b c0 2f 84 df 92
* 64 74 8e da 1a 4b a6 e3 1a c8 67 d3 52 58 a4 b7
* 54 7f c4 83 bf ad 1f fe
*/
unsigned long iv[2] = { RB(0xf0ede846), RB(0x4348bd62) };
unsigned long plain[2] = { RB(0x54686520), RB(0x756e6b6e) };
unsigned long cipher[2] = { RB(0xae0ee811), RB(0xdffdc8d2) };
unsigned long key[3] = { RB(0x6740231b), RB(0x6d1a7e0c), RB(0x929605c2) };
#endif
#define Plain(a) (plain[a] ^ iv[a])
#define Cipher(a) (cipher[a])
#define Key(a) (key[a])
#define Rotl3(x) (((x) << 3) | ((x) >> 29))
#define Rotl(x,n) (((x) << ((n)&0x1f)) | ((x) >> (32-((n)&0x1f))))
main() {
unsigned long Miss = 0x1;
unsigned long latency = 0;
// a production wrapper for this core would increment more than key[0]
for(latency=0,key[0] -= 100; Miss && (latency < 200); latency++, key[0]++)
#include "rc5-72core.h"
if(Miss) printf("Core is NOT correct\n");
else printf("Core IS correct, latency=%d\n",latency);
exit(0);
}
--------------------------- rc5-72core.h ---------------------------------------
/* John L. Bass, Copyright 2003 */
{
static int Lctr, Sctr;
unsigned long S00, S01, S02, S03, S04, S05, S06, S07, S08, S09;
unsigned long S10, S11, S12, S13, S14, S15, S16, S17, S18, S19;
unsigned long S20, S21, S22, S23, S24, S25, S26, S27, S28, S29;
unsigned long S30, S31, S32, S33, S34, S35, S36, S37, S38, S39;
unsigned long S40, S41, S42, S43, S44, S45, S46, S47, S48, S49;
unsigned long S50, S51, S52, S53, S54, S55, S56, S57, S58, S59;
unsigned long S60, S61, S62, S63, S64, S65, S66, S67, S68, S69;
unsigned long S70, S71, S72, S73, S74, S75, S76, S77;
unsigned long L00, L01, L02, L03, L04, L05, L06, L07, L08, L09;
unsigned long L10, L11, L12, L13, L14, L15, L16, L17, L18, L19;
unsigned long L20, L21, L22, L23, L24, L25, L26, L27, L28, L29;
unsigned long L30, L31, L32, L33, L34, L35, L36, L37, L38, L39;
unsigned long L40, L41, L42, L43, L44, L45, L46, L47, L48, L49;
unsigned long L50, L51, L52, L53, L54, L55, L56, L57, L58, L59;
unsigned long L60, L61, L62, L63, L64, L65, L66, L67, L68, L69;
unsigned long L70, L71, L72, L73, L74, L75, L76, L77, L78, L79;
unsigned long E00, E01, E02, E03, E04, E05, E06, E07, E08, E09;
unsigned long E10, E11, E12, E13, E14, E15, E16, E17, E18, E19;
unsigned long E20, E21, E22, E23, E24, E25, E26, E27, E28;
unsigned long SR00[26], SR01[26], SR02[26], SR03[26], SR04[26], SR05[26], SR06[26], SR07[26], SR08[26], SR09[26];
unsigned long SR10[26], SR11[26], SR12[26], SR13[26], SR14[26], SR15[26], SR16[26], SR17[26], SR18[26], SR19[26];
unsigned long SR20[26], SR21[26], SR22[26], SR23[26], SR24[26], SR25[26], SR26[26], SR27[26], SR28[26], SR29[26];
unsigned long SR30[26], SR31[26], SR32[26], SR33[26], SR34[26], SR35[26], SR36[26], SR37[26], SR38[26], SR39[26];
unsigned long SR40[26], SR41[26], SR42[26], SR43[26], SR44[26], SR45[26], SR46[26], SR47[26], SR48[26], SR49[26];
unsigned long SR50[26], SR51[26];
unsigned long ER01, ER02, ER03, ER04, ER05, ER06, ER07, ER08, ER09;
unsigned long ER10, ER11, ER12, ER13, ER14, ER15, ER16, ER17, ER18, ER19;
unsigned long ER20, ER21, ER22, ER23, ER24, ER25, ER26, ER27;
unsigned long LR01, LR02[3], LR03[3], LR04[3], LR05[3], LR06[3], LR07[3], LR08[3], LR09[3];
unsigned long LR10[3], LR11[3], LR12[3], LR13[3], LR14[3], LR15[3], LR16[3], LR17[3], LR18[3], LR19[3];
unsigned long LR20[3], LR21[3], LR22[3], LR23[3], LR24[3], LR25[3], LR26[3], LR27[3], LR28[3], LR29[3];
unsigned long LR30[3], LR31[3], LR32[3], LR33[3], LR34[3], LR35[3], LR36[3], LR37[3], LR38[3], LR39[3];
unsigned long LR40[3], LR41[3], LR42[3], LR43[3], LR44[3], LR45[3], LR46[3], LR47[3], LR48[3], LR49[3];
unsigned long LR50[3], LR51[3], LR52[3], LR53[3], LR54[3], LR55[3], LR56[3], LR57[3], LR58[3], LR59[3];
unsigned long LR60[3], LR61[3], LR62[3], LR63[3], LR64[3], LR65[3], LR66[3], LR67[3], LR68[3], LR69[3];
unsigned long LR70[3], LR71[3], LR72[3], LR73[3], LR74[3], LR75[3], LR76[3], LR77[3], LR78[3], LR79[3];
// Pipeline Stage 79, completion ----------------
E27 = E25 ^ Cipher(1);
E26 = ER24 ^ Cipher(0);
Miss = E26 & E27;
// Pipeline Stage 78, round 3 -------------------
S77 = Rotl3(SR51[Sctr] + S76 + L79);
E25 = Rotl(ER23 ^ E24, E24) + S77;
ER24 = E24;
// Pipeline Stage 77, round 3 -------------------
S76 = Rotl3(SR50[Sctr] + S75 + L78);
L79 = Rotl(LR76[Lctr] + S76 + L78, S76 + L78);
LR79[Lctr] = L79;
E24 = Rotl(ER22 ^ E23, E23) + S76;
ER23 = E23;
// Pipeline Stage 76, round 3 -------------------
S75 = Rotl3(SR49[Sctr] + S74 + L77);
L78 = Rotl(LR75[Lctr] + S75 + L77, S75 + L77);
LR78[Lctr] = L78;
E23 = Rotl(ER21 ^ E22, E22) + S75;
ER22 = E22;
// Pipeline Stage 75, round 3 -------------------
S74 = Rotl3(SR48[Sctr] + S73 + L76);
L77 = Rotl(LR74[Lctr] + S74 + L76, S74 + L76);
LR77[Lctr] = L77;
E22 = Rotl(ER20 ^ E21, E21) + S74;
ER21 = E21;
// Pipeline Stage 74, round 3 -------------------
S73 = Rotl3(SR47[Sctr] + S72 + L75);
L76 = Rotl(LR73[Lctr] + S73 + L75, S73 + L75);
LR76[Lctr] = L76;
E21 = Rotl(ER19 ^ E20, E20) + S73;
ER20 = E20;
// Pipeline Stage 73, round 3 -------------------
S72 = Rotl3(SR46[Sctr] + S71 + L74);
L75 = Rotl(LR72[Lctr] + S72 + L74, S72 + L74);
LR75[Lctr] = L75;
E20 = Rotl(ER18 ^ E19, E19) + S72;
ER19 = E19;
// Pipeline Stage 72, round 3 -------------------
S71 = Rotl3(SR45[Sctr] + S70 + L73);
L74 = Rotl(LR71[Lctr] + S71 + L73, S71 + L73);
LR74[Lctr] = L74;
E19 = Rotl(ER17 ^ E18, E18) + S71;
ER18 = E18;
// Pipeline Stage 71, round 3 -------------------
S70 = Rotl3(SR44[Sctr] + S69 + L72);
L73 = Rotl(LR70[Lctr] + S70 + L72, S70 + L72);
LR73[Lctr] = L73;
E18 = Rotl(ER16 ^ E17, E17) + S70;
ER17 = E17;
// Pipeline Stage 70, round 3 -------------------
S69 = Rotl3(SR43[Sctr] + S68 + L71);
L72 = Rotl(LR69[Lctr] + S69 + L71, S69 + L71);
LR72[Lctr] = L72;
E17 = Rotl(ER15 ^ E16, E16) + S69;
ER16 = E16;
// Pipeline Stage 69, round 3 -------------------
S68 = Rotl3(SR42[Sctr] + S67 + L70);
L71 = Rotl(LR68[Lctr] + S68 + L70, S68 + L70);
LR71[Lctr] = L71;
E16 = Rotl(ER14 ^ E15, E15) + S68;
ER15 = E15;
// Pipeline Stage 68, round 3 -------------------
S67 = Rotl3(SR41[Sctr] + S66 + L69);
L70 = Rotl(LR67[Lctr] + S67 + L69, S67 + L69);
LR70[Lctr] = L70;
E15 = Rotl(ER13 ^ E14, E14) + S67;
ER14 = E14;
// Pipeline Stage 67, round 3 -------------------
S66 = Rotl3(SR40[Sctr] + S65 + L68);
L69 = Rotl(LR66[Lctr] + S66 + L68, S66 + L68);
LR69[Lctr] = L69;
E14 = Rotl(ER12 ^ E13, E13) + S66;
ER13 = E13;
// Pipeline Stage 66, round 3 -------------------
S65 = Rotl3(SR39[Sctr] + S64 + L67);
L68 = Rotl(LR65[Lctr] + S65 + L67, S65 + L67);
LR68[Lctr] = L68;
E13 = Rotl(ER11 ^ E12, E12) + S65;
ER12 = E12;
// Pipeline Stage 65, round 3 -------------------
S64 = Rotl3(SR38[Sctr] + S63 + L66);
L67 = Rotl(LR64[Lctr] + S64 + L66, S64 + L66);
LR67[Lctr] = L67;
E12 = Rotl(ER10 ^ E11, E11) + S64;
ER11 = E11;
// Pipeline Stage 64, round 3 -------------------
S63 = Rotl3(SR37[Sctr] + S62 + L65);
L66 = Rotl(LR63[Lctr] + S63 + L65, S63 + L65);
LR66[Lctr] = L66;
E11 = Rotl(ER09 ^ E10, E10) + S63;
ER10 = E10;
// Pipeline Stage 63, round 3 -------------------
S62 = Rotl3(SR36[Sctr] + S61 + L64);
L65 = Rotl(LR62[Lctr] + S62 + L64, S62 + L64);
LR65[Lctr] = L65;
E10 = Rotl(ER08 ^ E09, E09) + S62;
ER09 = E09;
// Pipeline Stage 62, round 3 -------------------
S61 = Rotl3(SR35[Sctr] + S60 + L63);
L64 = Rotl(LR61[Lctr] + S61 + L63, S61 + L63);
LR64[Lctr] = L64;
E09 = Rotl(ER07 ^ E08, E08) + S61;
ER08 = E08;
// Pipeline Stage 61, round 3 -------------------
S60 = Rotl3(SR34[Sctr] + S59 + L62);
L63 = Rotl(LR60[Lctr] + S60 + L62, S60 + L62);
LR63[Lctr] = L63;
E08 = Rotl(ER06 ^ E07, E07) + S60;
ER07 = E07;
// Pipeline Stage 60, round 3 -------------------
S59 = Rotl3(SR33[Sctr] + S58 + L61);
L62 = Rotl(LR59[Lctr] + S59 + L61, S59 + L61);
LR62[Lctr] = L62;
E07 = Rotl(ER05 ^ E06, E06) + S59;
ER06 = E06;
// Pipeline Stage 59, round 3 -------------------
S58 = Rotl3(SR32[Sctr] + S57 + L60);
L61 = Rotl(LR58[Lctr] + S58 + L60, S58 + L60);
LR61[Lctr] = L61;
E06 = Rotl(ER04 ^ E05, E05) + S58;
ER05 = E05;
// Pipeline Stage 58, round 3 -------------------
S57 = Rotl3(SR31[Sctr] + S56 + L59);
L60 = Rotl(LR57[Lctr] + S57 + L59, S57 + L59);
LR60[Lctr] = L60;
E05 = Rotl(ER03 ^ E04, E04) + S57;
ER04 = E04;
// Pipeline Stage 57, round 3 -------------------
S56 = Rotl3(SR30[Sctr] + S55 + L58);
L59 = Rotl(LR56[Lctr] + S56 + L58, S56 + L58);
LR59[Lctr] = L59;
E04 = Rotl(ER02 ^ E03, E03) + S56;
ER03 = E03;
// Pipeline Stage 56, round 3 -------------------
S55 = Rotl3(SR29[Sctr] + S54 + L57);
L58 = Rotl(LR55[Lctr] + S55 + L57, S55 + L57);
LR58[Lctr] = L58;
E03 = Rotl(ER01 ^ E02, E02) + S55;
ER02 = E02;
// Pipeline Stage 55, round 3 -------------------
S54 = Rotl3(SR28[Sctr] + S53 + L56);
L57 = Rotl(LR54[Lctr] + S54 + L56, S54 + L56);
LR57[Lctr] = L57;
E02 = Rotl(E00 ^ E01, E01) + S54;
ER01 = E01;
// Pipeline Stage 54, round 3 -------------------
S53 = Rotl3(SR27[Sctr] + S52 + L55);
L56 = Rotl(LR53[Lctr] + S53 + L55, S53 + L55);
LR56[Lctr] = L56;
E01 = Plain(1) + S53;
E00 = Plain(0) + S52;
// Pipeline Stage 53, round 3 -------------------
S52 = Rotl3(SR26[Sctr] + S51 + L54);
L55 = Rotl(LR52[Lctr] + S52 + L54, S52 + L54);
LR55[Lctr] = L55;
// Pipeline Stage 52, round 2 -------------------
S51 = Rotl3(SR25[Sctr] + S50 + L53);
SR51[Sctr] = S51;
L54 = Rotl(LR51[Lctr] + S51 + L53, S51 + L53);
LR54[Lctr] = L54;
// Pipeline Stage 51, round 2 -------------------
S50 = Rotl3(SR24[Sctr] + S49 + L52);
SR50[Sctr] = S50;
L53 = Rotl(LR50[Lctr] + S50 + L52, S50 + L52);
LR53[Lctr] = L53;
// Pipeline Stage 50, round 2 -------------------
S49 = Rotl3(SR23[Sctr] + S48 + L51);
SR49[Sctr] = S49;
L52 = Rotl(LR49[Lctr] + S49 + L51, S49 + L51);
LR52[Lctr] = L52;
// Pipeline Stage 49, round 2 -------------------
S48 = Rotl3(SR22[Sctr] + S47 + L50);
SR48[Sctr] = S48;
L51 = Rotl(LR48[Lctr] + S48 + L50, S48 + L50);
LR51[Lctr] = L51;
// Pipeline Stage 48, round 2 -------------------
S47 = Rotl3(SR21[Sctr] + S46 + L49);
SR47[Sctr] = S47;
L50 = Rotl(LR47[Lctr] + S47 + L49, S47 + L49);
LR50[Lctr] = L50;
// Pipeline Stage 47, round 2 -------------------
S46 = Rotl3(SR20[Sctr] + S45 + L48);
SR46[Sctr] = S46;
L49 = Rotl(LR46[Lctr] + S46 + L48, S46 + L48);
LR49[Lctr] = L49;
// Pipeline Stage 46, round 2 -------------------
S45 = Rotl3(SR19[Sctr] + S44 + L47);
SR45[Sctr] = S45;
L48 = Rotl(LR45[Lctr] + S45 + L47, S45 + L47);
LR48[Lctr] = L48;
// Pipeline Stage 45, round 2 -------------------
S44 = Rotl3(SR18[Sctr] + S43 + L46);
SR44[Sctr] = S44;
L47 = Rotl(LR44[Lctr] + S44 + L46, S44 + L46);
LR47[Lctr] = L47;
// Pipeline Stage 44, round 2 -------------------
S43 = Rotl3(SR17[Sctr] + S42 + L45);
SR43[Sctr] = S43;
L46 = Rotl(LR43[Lctr] + S43 + L45, S43 + L45);
LR46[Lctr] = L46;
// Pipeline Stage 43, round 2 -------------------
S42 = Rotl3(SR16[Sctr] + S41 + L44);
SR42[Sctr] = S42;
L45 = Rotl(LR42[Lctr] + S42 + L44, S42 + L44);
LR45[Lctr] = L45;
// Pipeline Stage 42, round 2 -------------------
S41 = Rotl3(SR15[Sctr] + S40 + L43);
SR41[Sctr] = S41;
L44 = Rotl(LR41[Lctr] + S41 + L43, S41 + L43);
LR44[Lctr] = L44;
// Pipeline Stage 41, round 2 -------------------
S40 = Rotl3(SR14[Sctr] + S39 + L42);
SR40[Sctr] = S40;
L43 = Rotl(LR40[Lctr] + S40 + L42, S40 + L42);
LR43[Lctr] = L43;
// Pipeline Stage 40, round 2 -------------------
S39 = Rotl3(SR13[Sctr] + S38 + L41);
SR39[Sctr] = S39;
L42 = Rotl(LR39[Lctr] + S39 + L41, S39 + L41);
LR42[Lctr] = L42;
// Pipeline Stage 39, round 2 -------------------
S38 = Rotl3(SR12[Sctr] + S37 + L40);
SR38[Sctr] = S38;
L41 = Rotl(LR38[Lctr] + S38 + L40, S38 + L40);
LR41[Lctr] = L41;
// Pipeline Stage 38, round 2 -------------------
S37 = Rotl3(SR11[Sctr] + S36 + L39);
SR37[Sctr] = S37;
L40 = Rotl(LR37[Lctr] + S37 + L39, S37 + L39);
LR40[Lctr] = L40;
// Pipeline Stage 37, round 2 -------------------
S36 = Rotl3(SR10[Sctr] + S35 + L38);
SR36[Sctr] = S36;
L39 = Rotl(LR36[Lctr] + S36 + L38, S36 + L38);
LR39[Lctr] = L39;
// Pipeline Stage 36, round 2 -------------------
S35 = Rotl3(SR09[Sctr] + S34 + L37);
SR35[Sctr] = S35;
L38 = Rotl(LR35[Lctr] + S35 + L37, S35 + L37);
LR38[Lctr] = L38;
// Pipeline Stage 35, round 2 -------------------
S34 = Rotl3(SR08[Sctr] + S33 + L36);
SR34[Sctr] = S34;
L37 = Rotl(LR34[Lctr] + S34 + L36, S34 + L36);
LR37[Lctr] = L37;
// Pipeline Stage 34, round 2 -------------------
S33 = Rotl3(SR07[Sctr] + S32 + L35);
SR33[Sctr] = S33;
L36 = Rotl(LR33[Lctr] + S33 + L35, S33 + L35);
LR36[Lctr] = L36;
// Pipeline Stage 33, round 2 -------------------
S32 = Rotl3(SR06[Sctr] + S31 + L34);
SR32[Sctr] = S32;
L35 = Rotl(LR32[Lctr] + S32 + L34, S32 + L34);
LR35[Lctr] = L35;
// Pipeline Stage 32, round 2 -------------------
S31 = Rotl3(SR05[Sctr] + S30 + L33);
SR31[Sctr] = S31;
L34 = Rotl(LR31[Lctr] + S31 + L33, S31 + L33);
LR34[Lctr] = L34;
// Pipeline Stage 31, round 2 -------------------
S30 = Rotl3(SR04[Sctr] + S29 + L32);
SR30[Sctr] = S30;
L33 = Rotl(LR30[Lctr] + S30 + L32, S30 + L32);
LR33[Lctr] = L33;
// Pipeline Stage 30, round 2 -------------------
S29 = Rotl3(SR03[Sctr] + S28 + L31);
SR29[Sctr] = S29;
L32 = Rotl(LR29[Lctr] + S29 + L31, S29 + L31);
LR32[Lctr] = L32;
// Pipeline Stage 29, round 2 -------------------
S28 = Rotl3(SR02[Sctr] + S27 + L30);
SR28[Sctr] = S28;
L31 = Rotl(LR28[Lctr] + S28 + L30, S28 + L30);
LR31[Lctr] = L31;
// Pipeline Stage 28, round 2 -------------------
S27 = Rotl3(SR01[Sctr] + S26 + L29);
SR27[Sctr] = S27;
L30 = Rotl(LR27[Lctr] + S27 + L29, S27 + L29);
LR30[Lctr] = L30;
// Pipeline Stage 27, round 2 -------------------
S26 = Rotl3(SR00[Sctr] + S25 + L28);
SR26[Sctr] = S26;
L29 = Rotl(LR26[Lctr] + S26 + L28, S26 + L28);
LR29[Lctr] = L29;
// Pipeline Stage 26, round 1 -------------------
S25 = Rotl3(0x2b4c3474 + S24 + L27);
SR25[Sctr] = S25;
L28 = Rotl(LR25[Lctr] + S25 + L27, S25 + L27);
LR28[Lctr] = L28;
// Pipeline Stage 25, round 1 -------------------
S24 = Rotl3(0x8d14babb + S23 + L26);
SR24[Sctr] = S24;
L27 = Rotl(LR24[Lctr] + S24 + L26, S24 + L26);
LR27[Lctr] = L27;
// Pipeline Stage 24, round 1 -------------------
S23 = Rotl3(0xeedd4102 + S22 + L25);
SR23[Sctr] = S23;
L26 = Rotl(LR23[Lctr] + S23 + L25, S23 + L25);
LR26[Lctr] = L26;
// Pipeline Stage 23, round 1 -------------------
S22 = Rotl3(0x50a5c749 + S21 + L24);
SR22[Sctr] = S22;
L25 = Rotl(LR22[Lctr] + S22 + L24, S22 + L24);
LR25[Lctr] = L25;
// Pipeline Stage 22, round 1 -------------------
S21 = Rotl3(0xb26e4d90 + S20 + L23);
SR21[Sctr] = S21;
L24 = Rotl(LR21[Lctr] + S21 + L23, S21 + L23);
LR24[Lctr] = L24;
// Pipeline Stage 21, round 1 -------------------
S20 = Rotl3(0x1436d3d7 + S19 + L22);
SR20[Sctr] = S20;
L23 = Rotl(LR20[Lctr] + S20 + L22, S20 + L22);
LR23[Lctr] = L23;
// Pipeline Stage 20, round 1 -------------------
S19 = Rotl3(0x75ff5a1e + S18 + L21);
SR19[Sctr] = S19;
L22 = Rotl(LR19[Lctr] + S19 + L21, S19 + L21);
LR22[Lctr] = L22;
// Pipeline Stage 19, round 1 -------------------
S18 = Rotl3(0xd7c7e065 + S17 + L20);
SR18[Sctr] = S18;
L21 = Rotl(LR18[Lctr] + S18 + L20, S18 + L20);
LR21[Lctr] = L21;
// Pipeline Stage 18, round 1 -------------------
S17 = Rotl3(0x399066ac + S16 + L19);
SR17[Sctr] = S17;
L20 = Rotl(LR17[Lctr] + S17 + L19, S17 + L19);
LR20[Lctr] = L20;
// Pipeline Stage 17, round 1 -------------------
S16 = Rotl3(0x9b58ecf3 + S15 + L18);
SR16[Sctr] = S16;
L19 = Rotl(LR16[Lctr] + S16 + L18, S16 + L18);
LR19[Lctr] = L19;
// Pipeline Stage 16, round 1 -------------------
S15 = Rotl3(0xfd21733a + S14 + L17);
SR15[Sctr] = S15;
L18 = Rotl(LR15[Lctr] + S15 + L17, S15 + L17);
LR18[Lctr] = L18;
// Pipeline Stage 15, round 1 -------------------
S14 = Rotl3(0x5ee9f981 + S13 + L16);
SR14[Sctr] = S14;
L17 = Rotl(LR14[Lctr] + S14 + L16, S14 + L16);
LR17[Lctr] = L17;
// Pipeline Stage 14, round 1 -------------------
S13 = Rotl3(0xc0b27fc8 + S12 + L15);
SR13[Sctr] = S13;
L16 = Rotl(LR13[Lctr] + S13 + L15, S13 + L15);
LR16[Lctr] = L16;
// Pipeline Stage 13, round 1 -------------------
S12 = Rotl3(0x227b060f + S11 + L14);
SR12[Sctr] = S12;
L15 = Rotl(LR12[Lctr] + S12 + L14, S12 + L14);
LR15[Lctr] = L15;
// Pipeline Stage 12, round 1 -------------------
S11 = Rotl3(0x84438c56 + S10 + L13);
SR11[Sctr] = S11;
L14 = Rotl(LR11[Lctr] + S11 + L13, S11 + L13);
LR14[Lctr] = L14;
// Pipeline Stage 11, round 1 -------------------
S10 = Rotl3(0xe60c129d + S09 + L12);
SR10[Sctr] = S10;
L13 = Rotl(LR10[Lctr] + S10 + L12, S10 + L12);
LR13[Lctr] = L13;
// Pipeline Stage 10, round 1 -------------------
S09 = Rotl3(0x47d498e4 + S08 + L11);
SR09[Sctr] = S09;
L12 = Rotl(LR09[Lctr] + S09 + L11, S09 + L11);
LR12[Lctr] = L12;
// Pipeline Stage 9, round 1 -------------------
S08 = Rotl3(0xa99d1f2b + S07 + L10);
SR08[Sctr] = S08;
L11 = Rotl(LR08[Lctr] + S08 + L10, S08 + L10);
LR11[Lctr] = L11;
// Pipeline Stage 8, round 1 -------------------
S07 = Rotl3(0x0b65a572 + S06 + L09);
SR07[Sctr] = S07;
L10 = Rotl(LR07[Lctr] + S07 + L09, S07 + L09);
LR10[Lctr] = L10;
// Pipeline Stage 7, round 1 -------------------
S06 = Rotl3(0x6d2e2bb9 + S05 + L08);
SR06[Sctr] = S06;
L09 = Rotl(LR06[Lctr] + S06 + L08, S06 + L08);
LR09[Lctr] = L09;
// Pipeline Stage 6, round 1 -------------------
S05 = Rotl3(0xcef6b200 + S04 + L07);
SR05[Sctr] = S05;
L08 = Rotl(LR05[Lctr] + S05 + L07, S05 + L07);
LR08[Lctr] = L08;
// Pipeline Stage 5, round 1 -------------------
S04 = Rotl3(0x30bf3847 + S03 + L06);
SR04[Sctr] = S04;
L07 = Rotl(LR04[Lctr] + S04 + L06, S04 + L06);
LR07[Lctr] = L07;
// Pipeline Stage 4, round 1 -------------------
S03 = Rotl3(0x9287be8e + S02 + L05);
SR03[Sctr] = S03;
L06 = Rotl(LR03[Lctr] + S03 + L05, S03 + L05);
LR06[Lctr] = L06;
// Pipeline Stage 3, round 1 -------------------
S02 = Rotl3(0xf45044d5 + S01 + L04);
SR02[Sctr] = S02;
L05 = Rotl(LR02[Lctr] + S02 + L04, S02 + L04);
LR05[Lctr] = L05;
// Pipeline Stage 2, round 1 -------------------
S01 = Rotl3(0x5618cb1c + S00 + L03);
SR01[Sctr] = S01;
L04 = Rotl(LR01 + S01 + L03, S01 + L03);
LR04[Lctr] = L04;
// Pipeline Stage 1, round 1 -------------------
S00 = Rotl3(0xb7e15163);
SR00[Sctr] = S00;
L03 = Rotl(L00 + S00, S00);
LR03[Lctr] = L03;
LR01 = L01;
// Pipeline Stage 0, round 1 -------------------
L02 = Key(2);
LR02[Lctr] = L02;
L01 = Key(1);
L00 = Key(0);
Sctr = ++Sctr % 26;
Lctr = ++Lctr % 3;
//#include "72CheckSbox.h"
//#include "72CheckEterms.h"
}
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