Suggestions for FPGA RC5-72 core work verification?

Dan made a rather lengthy suggestion on how to verify correct clients
on processor based platforms, part of which is valid here. The biggest
difference is that for most FPGA cores, adding an additional stage at
the end to generate a CRC or Hash of the solution space is reasonable,
trival and affects performance little, if at all (other than requiring
a few dozen LUTs).

I'd like to suggest that a simple running XOR of the the generated test
cipher text and/or last SBox is probably enough, either as 32 bits
or 64 bits. This would make the "residual" independent of counter
order, and be reasonably inexpensive to also implement on processor
based clients, to verify an FPGA core's correctness. This residual would
be returned to the key server and logged.

Dan probably has better ideas, as will others, so this is probably a
good time to air them.

Have fun,
John
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