Re: Suggestions for FPGA RC5-72 core work verification?

Hi Dan & Guys,

I kinda thought a running Xor sum would be enough too, for the same
reasons. Interesting we were writing at the same time yesterday
morning :)

I think it's probably better than the partial match, since it will also
catch processing glitches if a core/fpga is pushing speed/heat a bit
and not being accurate.

I started an octal PCB layout yesterday using a PCI 64bit 3.3V based
design. The layout is setup as a hypercube with unbalanced bisection
bandwidth. FPGA's are mirrored on both sides of the board, will all
matching IOs connected. On the shared edges, a little over 60 lines
are cross connected between 4 FPGAs as a 2D mesh in each direction.
The thru board connections are a few mm, low inductance and capacitance,
and should support max pin toggle rates. The mesh connections have
4 pins connected each, with two vias at both ends, and about a cm
in the cross connect which should hold the wire under a 1/4 wave length
for reasonable pin toggle rates. Due to fanout, the toggle rates will
be a bit slower due to the additional capacitance. I may tighten this
up a bit if it proves a problem, I wanted to get a few bypass caps along
the shared edge. May also remove the via's, and make the connections
dedicated top and bottom. Decision is open to group concensus.

Have all the major data paths done, still need to work on configuration
and power. The layout is being done in PCB-20050315 (pcb available on
sourceforge). I will probably svn checkin the pcb layout under the FpgaC
project shortly (or sooner if someone wants a peek at the work in progress).

Have fun,
John
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