Re: The market of ASICs (One GigaKey / Second?)

jbass-/[email protected] writes:
> There is a register per LUT, and very big FPGA's have around 20-50K
> luts/registers. So 500K LUT's would require a few chips cascaded for
> a solution.

Xilinx XC2V10000 have a CLB array of 128 by 120, with 8 LUTs per CLB.

	128*120*8 = 122,880 LUTs with registers

with a price tag of something around $0.10/LUT in modest volumes.

Xilinx XC2V1000's have a CLB array of 40 by 32, with 8 LUTs per CLB.

	40*32*8 = 10,240 LUTs with registers

with a price tag of something around $0.034/LUT in modest volumes.

Folding the design around LUT based RAMs makes the design significantly
smaller in terms of LUT's, and probably can be easily targeted to
these more economical devices.

On ebay devices this size can frequently be had as surplus or pulls
at affordable prices.

John
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