Re: RC5 on FPGA, updated results

Martin Klingensmith <[email protected]> Thu, 22 Feb 2007 09:43:44 -0500
Newsgroups gmane.comp.distributed-net.hardware
Message-ID <[email protected]>
Hi John,
I don't have any respectable implementation yet. I just have raw Verilog
code that tests 1 key. I haven't figure out how to account for the
S-table delays yet.
--
Martin K

John L. Bass wrote:
> Hi Martin,
>
> What's your keyrate and Xpower numbers for the XC3S2000 parts?
>
> Have fun!
> John
>
>   

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