Re: RC5 core update

Hi Martin,

I have to admit, that unrolled pipelined cores can be a bit frustrating
to debug when you get the retiming off. A few months back I posted the
C version which is properly unrolled and retimed. You should be able to
align that to your Verilog version as one starting point.

In your test bench, check for the expected corrrect values, and flag when
they occur, noting the clock count, starting with the first rounds. When
you get the retiming right, the correct values will pop up in sequence.
If the example I posted doesn't have that debugging aid, I'll post another
that does.

Have fun!!
John
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