Re: The market of ASICs (One GigaKey / Second?)

"Dan Oetting" <[email protected]>
Newsgroups gmane.comp.distributed-net.hardware
Message-ID <[email protected]>
You don't need a boatload of registers to pipeline this function. Just 
regenerate the intermediate results as needed. You'll need to do about 
twice the work but with no register files it will be a fraction of the 
size.

Of course, I still don't think it's worth building. Why don't you just 
sell the stat points directly?


On Jul 14, 2004, at 10:58 AM, Jim C. Nasby wrote:

> A half-million bits of register space doesn't seem that much for a 
> large
> FPGA, but I've been out of the EE business for almost 10 years now... 
> :)
>
> Can stages be combined? If they could it should cut down on the number
> of registers.
>
> On Tue, Jul 13, 2004 at 11:33:53PM +0200, Michael Meeuwisse wrote:
>> Every stage has a different key, thus a different expanded keytable 
>> (832
>> bits). Since we have about 600 stages (449200 bits, or 62KiB), it 
>> sounds to
>> me we're going to need a lot of internal registers. Even that much 
>> that I
>> started looking at external memory (not the entire keytable is needed 
>> every
>> stage). And ASICs.
>>
>> Hope that answers your question. - wacco
>>
>>> If you're pipelining, why do you need memory for any of the 
>>> intermediate
>>> stuff?
>>> --
>>> Jim C. Nasby, Database Consultant                  [email protected]
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> -- 
> Jim C. Nasby, Database Consultant                  [email protected]
> Member: Triangle Fraternity, Sports Car Club of America
> Give your computer some brain candy! www.distributed.net Team #1828
>
> Windows: "Where do you want to go today?"
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> FreeBSD: "Are you guys coming, or what?"
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