Re: The market of ASICs (One GigaKey / Second?)
jbass-/[email protected]
| Newsgroups | gmane.comp.distributed-net.hardware |
|---|---|
| Message-ID | <[email protected]> |
A quick ascii graphic of my previous text.
With things unrolled into a pipeline of adders and barrel shifter functional
blocks, you have this matrix structure with 26 stages horizontal, and 3 rounds
coupled vertically with 26 bit long shift register fifos to synchornize the
S terms:
Ctr
|
v
------ ------ ------ ...... ------ ------ ------
| 1 |-->| 2 |-->| 3 |--> -->| 24 |-->| 25 |-->| 26 |-->AB1
------ ------ ------ ...... ------ ------ ------
# # # # # #
------ ------ ------ ...... ------ ------ ------
AB1-->| 1 |-->| 2 |-->| 3 |--> -->| 24 |-->| 25 |-->| 26 |-->AB2
------ ------ ------ ...... ------ ------ ------
# # # # # #
------ ------ ------ ...... ------ ------ ------
AB2-->| 1 |-->| 2 |-->| 3 |--> -->| 24 |-->| 25 |-->| 26 |
------ ------ ------ ...... ------ ------ ------
Where each box is the logic for a stage, and '#' is a fifo connection
vertically. It takes 78 clocks to test first key, and one key per clock
thereafter.
Hope that makes a bit more sense.
John
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