Re: OGR-NG on Xeon Phi?

Joseph Kaye <[email protected]> Thu, 13 Dec 2012 15:04:51 -0600
Newsgroups gmane.comp.distributed-net.rc5
Message-ID <[email protected]>
If this article from semiaccurate.com is semi accurate itself, it looks 
like not much, if any porting will be needed to use the Xeon Phi with dnetc:

http://semiaccurate.com/2012/11/13/what-will-intel-xeon-phi-do-to-the-gpgpu-market/#.UMo_UFelsYo

Getting back to the topic at hand we have Intel's new Xeon Phi 
accelerator. It was originally a project called Larrabee that Intel 
intended to be a GPU based on x86. That goal, umm, didn't work out 
exactly as intended, and the project was reoriented to be a compute 
accelerator. The delays meant the first generation was DOA, mainly used 
as a software development tool to work the bugs out. The bugs were more 
Intel's, not the customers, and the third generation part showed a 
marked improvement in most areas. That part is what was released 
yesterday as Knights Corner/MIC/Xeon Phi.

The biggest drawback to its use as a GPU was the layout, basically a 
shared nothing cluster of x86 cores with a massively wide vector engine 
bolted to each one. It sort of makes sense if you think about it, but 
the work involved with chaining Seymour Cray's proverbial 1024 chickens 
to a plow comes to mind in making Phi do GPU work. The architecture is 
unquestionably more flexible than a GPU but also takes more to focus on 
that task that purpose built hardware. That same drawback however makes 
it a much better compute accelerator than a GPU, there are times when 
the chickens win.
*
**Intel wisely made Phi look like a dirt standard rack of x86 servers to 
the software.* They can talk TCP/IP over PCIe, so the communications 
protocols are what you would expect. In general, the chip is purpose 
built to look like an MPI cluster to existing code. In case you don't 
follow parallel programming APIs closely, MPI is by far the most widely 
known and used way to program parallel code. Everyone knows it, and 
everyone who has done parallel programming is at least familiar with the 
paradigm.

Phi also runs Linux, a mildly tweaked but vanilla kernel that Intel 
claims will be merged in to the main kernel line in short order. You can 
SSH in to it, run code on it, and do everything you want just like a 
standard HPC box running Linux. Since Microsoft has about zero 
marketshare in the HPC and supercomputer space, this is a welcome and 
familiar way to do things for everyone involved.



--Joseph











On 12/12/2012 12:30 AM, [email protected] wrote:
> Good Morning!
>
> Just for Interest:
>
> As there is no possibility to port OGR (usefull) to CUDA/OpenCL,
> does someone know if it would possible to Port OGR-NG to the Xeon Phi accelerator-card? For me as a layman the Intel MIC-specs reads as it would be possible as the Phi is equiped with modified x86-Cores, relativly large Cache per core, high memory bandwith per Core etc.
> Additional, the Phi-Cores are equipped with 512Bit SIMD-Units. I dont know any detail of their architecture or commandset, but maybe this could be a great benefit for OGR?
>
> My question in short:
> If the Xeon Phi is avaiable on stock, would it be usefull for OGR and would there be someone who port the client?
>
> This would especialy interesting if there will be an OGR-28-Project
>   that could benefit from Phi aswell.
>
> Thank you in advance,
>
> Grodahn
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