CUDA clients need recompiling for newer GPUs

Greg Childers <jgchilders-j9/[email protected]> Sat, 18 Jan 2014 02:53:11 -0800
Newsgroups gmane.comp.distributed-net.rc5
Message-ID <CAPOvAR4j5ZZvF-QEAGBS_KLqK4kCiZe0OH1OFn2FQQNvDA_2QQ@mail.gmail.com>
--===============5962618246133777625==
Content-Type: multipart/alternative; boundary=f46d043bdf6afcc4d404f03c76bb

--f46d043bdf6afcc4d404f03c76bb
Content-Type: text/plain; charset=ISO-8859-1

Hi,

The newer CUDA sm_35 GPUs such as the GTX Titan and Tesla K20/K40 have a
funnel shift instruction, which can be used as a 32-bit rotate.  No code
changes are necessary.  The compiler recognizes the two shifts and or as a
rotate, and does the right thing.  Here are the results of my testing on a
Tesla K20.

Current client:

dnetc v2.9108-517-CTR-10070312 for CUDA 3.1 on Linux (Linux 2.6.32-279.14.1
...

Please provide the *entire* version descriptor when submitting bug reports.

The distributed.net bug report pages are at http://bugs.distributed.net/


[Jan 18 10:47:30 UTC] RC5-72: using core #0 (CUDA 1-pipe 64-thd).

[Jan 18 10:47:37 UTC] RC5-72: Benchmark for core #0 (CUDA 1-pipe 64-thd)

                      0.00:00:04.63 [937,151,615 keys/sec]

[Jan 18 10:47:37 UTC] RC5-72: using core #1 (CUDA 1-pipe 128-thd).

[Jan 18 10:47:44 UTC] RC5-72: Benchmark for core #1 (CUDA 1-pipe 128-thd)

                      0.00:00:04.44 [976,631,543 keys/sec]

[Jan 18 10:47:44 UTC] RC5-72: using core #2 (CUDA 1-pipe 256-thd).

[Jan 18 10:47:50 UTC] RC5-72: Benchmark for core #2 (CUDA 1-pipe 256-thd)

                      0.00:00:04.42 [981,795,666 keys/sec]

[Jan 18 10:47:50 UTC] RC5-72: using core #3 (CUDA 2-pipe 64-thd).

[Jan 18 10:47:57 UTC] RC5-72: Benchmark for core #3 (CUDA 2-pipe 64-thd)

                      0.00:00:04.74 [914,549,002 keys/sec]

[Jan 18 10:47:57 UTC] RC5-72: using core #4 (CUDA 2-pipe 128-thd).

[Jan 18 10:48:04 UTC] RC5-72: Benchmark for core #4 (CUDA 2-pipe 128-thd)

                      0.00:00:04.58 [948,142,344 keys/sec]

[Jan 18 10:48:04 UTC] RC5-72: using core #5 (CUDA 2-pipe 256-thd).

[Jan 18 10:48:10 UTC] RC5-72: Benchmark for core #5 (CUDA 2-pipe 256-thd)

                      0.00:00:04.40 [985,609,646 keys/sec]

[Jan 18 10:48:10 UTC] RC5-72: using core #6 (CUDA 4-pipe 64-thd).

[Jan 18 10:48:17 UTC] RC5-72: Benchmark for core #6 (CUDA 4-pipe 64-thd)

                      0.00:00:04.51 [962,502,541 keys/sec]

[Jan 18 10:48:17 UTC] RC5-72: using core #7 (CUDA 4-pipe 128-thd).

[Jan 18 10:48:23 UTC] RC5-72: Benchmark for core #7 (CUDA 4-pipe 128-thd)

                      0.00:00:04.40 [986,996,612 keys/sec]

[Jan 18 10:48:23 UTC] RC5-72: using core #8 (CUDA 4-pipe 256-thd).

[Jan 18 10:48:30 UTC] RC5-72: Benchmark for core #8 (CUDA 4-pipe 256-thd)



                      0.00:00:04.36 [995,250,114 keys/sec]

[Jan 18 10:48:30 UTC] RC5-72: using core #9 (CUDA 1-pipe 64-thd busy wait).

[Jan 18 10:48:36 UTC] RC5-72: Benchmark for core #9 (CUDA 1-pipe 64-thd
busy wait)


                      0.00:00:04.53 [957,125,645 keys/sec]

[Jan 18 10:48:36 UTC] RC5-72: using core #10 (CUDA 1-pipe 64-thd sleep
100us).

[Jan 18 10:48:43 UTC] RC5-72: Benchmark for core #10 (CUDA 1-pipe 64-thd
sleep 100us)


                      0.00:00:04.58 [947,487,144 keys/sec]

[Jan 18 10:48:43 UTC] RC5-72: using core #11 (CUDA 1-pipe 64-thd sleep
dynamic).

[Jan 18 10:48:50 UTC] RC5-72: Benchmark for core #11 (CUDA 1-pipe 64-thd
sleep dynamic)


                      0.00:00:04.57 [949,532,041 keys/sec]

[Jan 18 10:48:50 UTC] RC5-72 benchmark summary :

                      Default core : #0 (CUDA 1-pipe 64-thd)

                      Fastest core : #8 (CUDA 4-pipe 256-thd)


Recompiled client:

dnetc v2.9110-519-CTR-11072023 for CUDA on Linux (Linux 2.6.32-279.14.1.el6
...

Please provide the *entire* version descriptor when submitting bug reports.

The distributed.net bug report pages are at http://bugs.distributed.net/


[Jan 18 10:50:19 UTC] RC5-72: using core #0 (CUDA 1-pipe 64-thd).

[Jan 18 10:50:24 UTC] RC5-72: Benchmark for core #0 (CUDA 1-pipe 64-thd)

                      0.00:00:03.19 [1,367,772,924 keys/sec]

[Jan 18 10:50:24 UTC] RC5-72: using core #1 (CUDA 1-pipe 128-thd).

[Jan 18 10:50:29 UTC] RC5-72: Benchmark for core #1 (CUDA 1-pipe 128-thd)

                      0.00:00:03.12 [1,395,317,272 keys/sec]

[Jan 18 10:50:29 UTC] RC5-72: using core #2 (CUDA 1-pipe 256-thd).

[Jan 18 10:50:35 UTC] RC5-72: Benchmark for core #2 (CUDA 1-pipe 256-thd)

                      0.00:00:03.09 [1,409,888,624 keys/sec]

[Jan 18 10:50:35 UTC] RC5-72: using core #3 (CUDA 2-pipe 64-thd).

[Jan 18 10:50:40 UTC] RC5-72: Benchmark for core #3 (CUDA 2-pipe 64-thd)

                      0.00:00:03.15 [1,383,760,581 keys/sec]

[Jan 18 10:50:40 UTC] RC5-72: using core #4 (CUDA 2-pipe 128-thd).

[Jan 18 10:50:45 UTC] RC5-72: Benchmark for core #4 (CUDA 2-pipe 128-thd)

                      0.00:00:03.04 [1,435,289,273 keys/sec]

[Jan 18 10:50:45 UTC] RC5-72: using core #5 (CUDA 2-pipe 256-thd).

[Jan 18 10:50:50 UTC] RC5-72: Benchmark for core #5 (CUDA 2-pipe 256-thd)

                      0.00:00:03.00 [1,454,768,816 keys/sec]

[Jan 18 10:50:50 UTC] RC5-72: using core #6 (CUDA 4-pipe 64-thd).

[Jan 18 10:50:55 UTC] RC5-72: Benchmark for core #6 (CUDA 4-pipe 64-thd)

                      0.00:00:03.11 [1,402,262,966 keys/sec]

[Jan 18 10:50:55 UTC] RC5-72: using core #7 (CUDA 4-pipe 128-thd).

[Jan 18 10:51:00 UTC] RC5-72: Benchmark for core #7 (CUDA 4-pipe 128-thd)

                      0.00:00:03.08 [1,416,234,138 keys/sec]

[Jan 18 10:51:00 UTC] RC5-72: using core #8 (CUDA 4-pipe 256-thd).

[Jan 18 10:51:05 UTC] RC5-72: Benchmark for core #8 (CUDA 4-pipe 256-thd)



                      0.00:00:03.05 [1,429,372,665 keys/sec]

[Jan 18 10:51:05 UTC] RC5-72: using core #9 (CUDA 1-pipe 64-thd busy wait).

[Jan 18 10:51:11 UTC] RC5-72: Benchmark for core #9 (CUDA 1-pipe 64-thd
busy wait)


                      0.00:00:03.14 [1,386,448,528 keys/sec]

[Jan 18 10:51:11 UTC] RC5-72: using core #10 (CUDA 1-pipe 64-thd sleep
100us).

[Jan 18 10:51:16 UTC] RC5-72: Benchmark for core #10 (CUDA 1-pipe 64-thd
sleep 100us)


                      0.00:00:03.29 [1,324,972,176 keys/sec]

[Jan 18 10:51:16 UTC] RC5-72: using core #11 (CUDA 1-pipe 64-thd sleep
dynamic).

[Jan 18 10:51:21 UTC] RC5-72: Benchmark for core #11 (CUDA 1-pipe 64-thd
sleep dynamic)


                      0.00:00:03.18 [1,371,027,270 keys/sec]

[Jan 18 10:51:21 UTC] RC5-72 benchmark summary :

                      Default core : #0 (CUDA 1-pipe 64-thd)

                      Fastest core : #5 (CUDA 2-pipe 256-thd)


You can easily compile for all current architectures by removing the ptx
and cubin lines, and compiling with

NVCC = /usr/local/cuda/bin/nvcc --generate-code arch=compute_10,code=sm_10
--generate-code arch=compute_20,code=sm_20 --generate-code
arch=compute_30,code=sm_30 --generate-code arch=compute_35,code=sm_35

Greg

--f46d043bdf6afcc4d404f03c76bb
Content-Type: text/html; charset=ISO-8859-1
Content-Transfer-Encoding: quoted-printable

<div dir=3D"ltr">Hi,<div><br></div><div>The newer CUDA sm_35 GPUs such as t=
he GTX Titan and Tesla K20/K40 have a funnel shift instruction, which can b=
e used as a 32-bit rotate. =A0No code changes are necessary. =A0The compile=
r recognizes the two shifts and or as a rotate, and does the right thing. =
=A0Here are the results of my testing on a Tesla K20.</div>
<div><br></div><div>Current client:</div><div>







<p class=3D"">dnetc v2.9108-517-CTR-10070312 for CUDA 3.1 on Linux (Linux 2=
.6.32-279.14.1 ...</p>
<p class=3D"">Please provide the *entire* version descriptor when submittin=
g bug reports.</p>
<p class=3D"">The <a href=3D"http://distributed.net">distributed.net</a> bu=
g report pages are at <a href=3D"http://bugs.distributed.net/">http://bugs.=
distributed.net/</a></p>
<p class=3D""><br></p>
<p class=3D"">[Jan 18 10:47:30 UTC] RC5-72: using core #0 (CUDA 1-pipe 64-t=
hd).</p>
<p class=3D"">[Jan 18 10:47:37 UTC] RC5-72: Benchmark for core #0 (CUDA 1-p=
ipe 64-thd)</p>
<p class=3D"">=A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 0.00:00:04.63 [93=
7,151,615 keys/sec]</p>
<p class=3D"">[Jan 18 10:47:37 UTC] RC5-72: using core #1 (CUDA 1-pipe 128-=
thd).</p>
<p class=3D"">[Jan 18 10:47:44 UTC] RC5-72: Benchmark for core #1 (CUDA 1-p=
ipe 128-thd)</p>
<p class=3D"">=A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 0.00:00:04.44 [97=
6,631,543 keys/sec]</p>
<p class=3D"">[Jan 18 10:47:44 UTC] RC5-72: using core #2 (CUDA 1-pipe 256-=
thd).</p>
<p class=3D"">[Jan 18 10:47:50 UTC] RC5-72: Benchmark for core #2 (CUDA 1-p=
ipe 256-thd)</p>
<p class=3D"">=A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 0.00:00:04.42 [98=
1,795,666 keys/sec]</p>
<p class=3D"">[Jan 18 10:47:50 UTC] RC5-72: using core #3 (CUDA 2-pipe 64-t=
hd).</p>
<p class=3D"">[Jan 18 10:47:57 UTC] RC5-72: Benchmark for core #3 (CUDA 2-p=
ipe 64-thd)</p>
<p class=3D"">=A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 0.00:00:04.74 [91=
4,549,002 keys/sec]</p>
<p class=3D"">[Jan 18 10:47:57 UTC] RC5-72: using core #4 (CUDA 2-pipe 128-=
thd).</p>
<p class=3D"">[Jan 18 10:48:04 UTC] RC5-72: Benchmark for core #4 (CUDA 2-p=
ipe 128-thd)</p>
<p class=3D"">=A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 0.00:00:04.58 [94=
8,142,344 keys/sec]</p>
<p class=3D"">[Jan 18 10:48:04 UTC] RC5-72: using core #5 (CUDA 2-pipe 256-=
thd).</p>
<p class=3D"">[Jan 18 10:48:10 UTC] RC5-72: Benchmark for core #5 (CUDA 2-p=
ipe 256-thd)</p>
<p class=3D"">=A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 0.00:00:04.40 [98=
5,609,646 keys/sec]</p>
<p class=3D"">[Jan 18 10:48:10 UTC] RC5-72: using core #6 (CUDA 4-pipe 64-t=
hd).</p>
<p class=3D"">[Jan 18 10:48:17 UTC] RC5-72: Benchmark for core #6 (CUDA 4-p=
ipe 64-thd)</p>
<p class=3D"">=A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 0.00:00:04.51 [96=
2,502,541 keys/sec]</p>
<p class=3D"">[Jan 18 10:48:17 UTC] RC5-72: using core #7 (CUDA 4-pipe 128-=
thd).</p>
<p class=3D"">[Jan 18 10:48:23 UTC] RC5-72: Benchmark for core #7 (CUDA 4-p=
ipe 128-thd)</p>
<p class=3D"">=A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 0.00:00:04.40 [98=
6,996,612 keys/sec]</p>
<p class=3D"">[Jan 18 10:48:23 UTC] RC5-72: using core #8 (CUDA 4-pipe 256-=
thd).</p>
<p class=3D"">[Jan 18 10:48:30 UTC] RC5-72: Benchmark for core #8 (CUDA 4-p=
ipe 256-thd)=A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0=
 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =
=A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0=
 =A0</p>
<p class=3D"">=A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 0.00:00:04.36 [99=
5,250,114 keys/sec]</p>
<p class=3D"">[Jan 18 10:48:30 UTC] RC5-72: using core #9 (CUDA 1-pipe 64-t=
hd busy wait).</p>
<p class=3D"">[Jan 18 10:48:36 UTC] RC5-72: Benchmark for core #9 (CUDA 1-p=
ipe 64-thd busy wait) =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =
=A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0=
 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0</p>
<p class=3D"">=A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 0.00:00:04.53 [95=
7,125,645 keys/sec]</p>
<p class=3D"">[Jan 18 10:48:36 UTC] RC5-72: using core #10 (CUDA 1-pipe 64-=
thd sleep 100us).</p>
<p class=3D"">[Jan 18 10:48:43 UTC] RC5-72: Benchmark for core #10 (CUDA 1-=
pipe 64-thd sleep 100us)=A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0=
 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =
=A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0</p>
<p class=3D"">=A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 0.00:00:04.58 [94=
7,487,144 keys/sec]</p>
<p class=3D"">[Jan 18 10:48:43 UTC] RC5-72: using core #11 (CUDA 1-pipe 64-=
thd sleep dynamic).</p>
<p class=3D"">[Jan 18 10:48:50 UTC] RC5-72: Benchmark for core #11 (CUDA 1-=
pipe 64-thd sleep dynamic)=A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =
=A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0=
 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0</p>
<p class=3D"">=A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 0.00:00:04.57 [94=
9,532,041 keys/sec]</p>
<p class=3D"">[Jan 18 10:48:50 UTC] RC5-72 benchmark summary :</p>
<p class=3D"">=A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 Default core : #0=
 (CUDA 1-pipe 64-thd)</p>
<p class=3D"">=A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 Fastest core : #8=
 (CUDA 4-pipe 256-thd)</p><p class=3D""><br></p><p class=3D"">Recompiled cl=
ient:</p><p class=3D"">dnetc v2.9110-519-CTR-11072023 for CUDA on Linux (Li=
nux 2.6.32-279.14.1.el6 ...</p>
<p class=3D"">Please provide the *entire* version descriptor when submittin=
g bug reports.</p><p class=3D"">The <a href=3D"http://distributed.net">dist=
ributed.net</a> bug report pages are at <a href=3D"http://bugs.distributed.=
net/">http://bugs.distributed.net/</a></p>
<p class=3D""><br></p><p class=3D"">[Jan 18 10:50:19 UTC] RC5-72: using cor=
e #0 (CUDA 1-pipe 64-thd).</p><p class=3D"">[Jan 18 10:50:24 UTC] RC5-72: B=
enchmark for core #0 (CUDA 1-pipe 64-thd)</p><p class=3D"">=A0 =A0 =A0 =A0 =
=A0 =A0 =A0 =A0 =A0 =A0 =A0 0.00:00:03.19 [1,367,772,924 keys/sec]</p>
<p class=3D"">[Jan 18 10:50:24 UTC] RC5-72: using core #1 (CUDA 1-pipe 128-=
thd).</p><p class=3D"">[Jan 18 10:50:29 UTC] RC5-72: Benchmark for core #1 =
(CUDA 1-pipe 128-thd)</p><p class=3D"">=A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =
=A0 =A0 0.00:00:03.12 [1,395,317,272 keys/sec]</p>
<p class=3D"">[Jan 18 10:50:29 UTC] RC5-72: using core #2 (CUDA 1-pipe 256-=
thd).</p><p class=3D"">[Jan 18 10:50:35 UTC] RC5-72: Benchmark for core #2 =
(CUDA 1-pipe 256-thd)</p><p class=3D"">=A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =
=A0 =A0 0.00:00:03.09 [1,409,888,624 keys/sec]</p>
<p class=3D"">[Jan 18 10:50:35 UTC] RC5-72: using core #3 (CUDA 2-pipe 64-t=
hd).</p><p class=3D"">[Jan 18 10:50:40 UTC] RC5-72: Benchmark for core #3 (=
CUDA 2-pipe 64-thd)</p><p class=3D"">=A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =
=A0 =A0 0.00:00:03.15 [1,383,760,581 keys/sec]</p>
<p class=3D"">[Jan 18 10:50:40 UTC] RC5-72: using core #4 (CUDA 2-pipe 128-=
thd).</p><p class=3D"">[Jan 18 10:50:45 UTC] RC5-72: Benchmark for core #4 =
(CUDA 2-pipe 128-thd)</p><p class=3D"">=A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =
=A0 =A0 0.00:00:03.04 [1,435,289,273 keys/sec]</p>
<p class=3D"">[Jan 18 10:50:45 UTC] RC5-72: using core #5 (CUDA 2-pipe 256-=
thd).</p><p class=3D"">[Jan 18 10:50:50 UTC] RC5-72: Benchmark for core #5 =
(CUDA 2-pipe 256-thd)</p><p class=3D"">=A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =
=A0 =A0 0.00:00:03.00 [1,454,768,816 keys/sec]</p>
<p class=3D"">[Jan 18 10:50:50 UTC] RC5-72: using core #6 (CUDA 4-pipe 64-t=
hd).</p><p class=3D"">[Jan 18 10:50:55 UTC] RC5-72: Benchmark for core #6 (=
CUDA 4-pipe 64-thd)</p><p class=3D"">=A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =
=A0 =A0 0.00:00:03.11 [1,402,262,966 keys/sec]</p>
<p class=3D"">[Jan 18 10:50:55 UTC] RC5-72: using core #7 (CUDA 4-pipe 128-=
thd).</p><p class=3D"">[Jan 18 10:51:00 UTC] RC5-72: Benchmark for core #7 =
(CUDA 4-pipe 128-thd)</p><p class=3D"">=A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =
=A0 =A0 0.00:00:03.08 [1,416,234,138 keys/sec]</p>
<p class=3D"">[Jan 18 10:51:00 UTC] RC5-72: using core #8 (CUDA 4-pipe 256-=
thd).</p><p class=3D"">[Jan 18 10:51:05 UTC] RC5-72: Benchmark for core #8 =
(CUDA 4-pipe 256-thd)=A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =
=A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0=
 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =
=A0 =A0 =A0 =A0</p>
<p class=3D"">=A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 0.00:00:03.05 [1,=
429,372,665 keys/sec]</p><p class=3D"">[Jan 18 10:51:05 UTC] RC5-72: using =
core #9 (CUDA 1-pipe 64-thd busy wait).</p><p class=3D"">[Jan 18 10:51:11 U=
TC] RC5-72: Benchmark for core #9 (CUDA 1-pipe 64-thd busy wait) =A0 =A0 =
=A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0=
 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =
=A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0</p>
<p class=3D"">=A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 0.00:00:03.14 [1,=
386,448,528 keys/sec]</p><p class=3D"">[Jan 18 10:51:11 UTC] RC5-72: using =
core #10 (CUDA 1-pipe 64-thd sleep 100us).</p><p class=3D"">[Jan 18 10:51:1=
6 UTC] RC5-72: Benchmark for core #10 (CUDA 1-pipe 64-thd sleep 100us)=A0 =
=A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0=
 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =
=A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0</p>
<p class=3D"">=A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 0.00:00:03.29 [1,=
324,972,176 keys/sec]</p><p class=3D"">[Jan 18 10:51:16 UTC] RC5-72: using =
core #11 (CUDA 1-pipe 64-thd sleep dynamic).</p><p class=3D"">[Jan 18 10:51=
:21 UTC] RC5-72: Benchmark for core #11 (CUDA 1-pipe 64-thd sleep dynamic)=
=A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0=
 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =
=A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0</p>
<p class=3D"">=A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 0.00:00:03.18 [1,=
371,027,270 keys/sec]</p><p class=3D"">[Jan 18 10:51:21 UTC] RC5-72 benchma=
rk summary :</p><p class=3D"">=A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 D=
efault core : #0 (CUDA 1-pipe 64-thd)</p><p class=3D"">


















































</p><p class=3D"">=A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0=A0Fastest cor=
e : #5 (CUDA 2-pipe 256-thd)</p><p class=3D""><br></p><p class=3D"">You can=
 easily compile for all current architectures by removing the ptx and cubin=
 lines, and compiling with</p>
<p class=3D"">







</p><p class=3D"">NVCC =3D /usr/local/cuda/bin/nvcc --generate-code arch=3D=
compute_10,code=3Dsm_10 --generate-code arch=3Dcompute_20,code=3Dsm_20 --ge=
nerate-code arch=3Dcompute_30,code=3Dsm_30 --generate-code arch=3Dcompute_3=
5,code=3Dsm_35</p>
<p class=3D"">Greg</p></div></div>

--f46d043bdf6afcc4d404f03c76bb--

--===============5962618246133777625==
Content-Type: text/plain; charset="us-ascii"
MIME-Version: 1.0
Content-Transfer-Encoding: 7bit
Content-Disposition: inline

_______________________________________________
rc5 mailing list
rc5-Ra3b/QYEcJ3d140v2zMXi0fjHoOT/h/[email protected]
http://lists.distributed.net/mailman/listinfo/rc5

--===============5962618246133777625==--