Re: Atomic Instruction Emulation

In COREMU, an atomic x86 instruction in the guest is mapped
to essentially the same instruction on the host for x86-on-x86 emulation.
 That is one of the techniques which enables COREMU to run each VCPU in a
separate host thread.

PS. The PPoPP paper on COREMU claims that the atomic instructions are
implemented using a different technique.  But that's not what is really
done in the code.

On Wed, Oct 3, 2012 at 8:55 AM, Stanislav <[email protected]> wrote:

> Exactly. This works ONLY under assumption that bochs emulated CPUs are
> multiplexed onto physical CPUs in a serial fashion.
>
> Stanislav
>
> -----Original Message-----
> From: Xin Tong [mailto:[email protected]]
> Sent: Wednesday, October 03, 2012 4:14 PM
> To: [email protected]
> Subject: [Bochs-developers] Atomic Instruction Emulation
>
> I am looking at how atomic instructions are emulated in bochs. it seems
> they
> are not emulated in an "atomic" way. i.e. for CMPXCHG_EdGdM. CMPXCHG_EdGdM
> is not atomic by itself, but with a lock prefix, it is atomic. but i do not
> see the lock prefix being checked here.  Maybe this works under the
> assumption that bochs emulated CPUs are multiplexed onto physical CPUs in a
> serial fashion.
>
> BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::CMPXCHG_EdGdM(bxInstruction_c
> *i) {
>   bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
>
>   Bit32u op1_32 = read_RMW_virtual_dword(i->seg(), eaddr);
>   Bit32u diff_32 = EAX - op1_32;
>   SET_FLAGS_OSZAPC_SUB_32(EAX, op1_32, diff_32);
>
>   if (diff_32 == 0) {  // if accumulator == dest
>     // dest <-- src
>     write_RMW_virtual_dword(BX_READ_32BIT_REG(i->nnn()));
>   }
>   else {
>     // accumulator <-- dest
>     RAX = op1_32;
>   }
>
>   BX_NEXT_INSTR(i);
> }
>
>
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