Re: SFENCE is an SSE instruction

I used Intel Software Developers Manual as reference. Even in latest 045
release it still says that SFENCE require SSE2 otherwise it will #UD.
But seems that you are right, I see many references in the web (including
wiki) that SFENCE was introduced with SSE and not with SSE2.
Looks like it is another bug in the SDM.
I sent SDM fix request to Intel and going to push your patch now.

Thanks,
Stanislav

-----Original Message-----
From: bl0 [mailto:[email protected]] 
Sent: Sunday, January 20, 2013 11:08 AM
To: [email protected]
Subject: [Bochs-developers] SFENCE is an SSE instruction

When Bochs 2.6 is configured to emulate "p3_katmai" CPU with SSE and without
SSE2, Linux fails at boot. Linux detects SSE support and tries to use some
SSE-optimized code (in this case, xor function when initializing RAID
support). The instruction which fails is SFENCE. Bochs only emulates SFENCE
if SSE2 is enabled. Quick search shows that SFENCE is part of the first SSE
instruction set.

Bochs source code, file cpu/ia_opcodes.h, line:
bx_define_opcode(BX_IA_SFENCE, &BX_CPU_C::BxError, &BX_CPU_C::NOP,
BX_ISA_SSE2, BX_SRC_NONE, BX_SRC_NONE, BX_SRC_NONE, BX_SRC_NONE, 0)

Changing BX_ISA_SSE2 to BX_ISA_SSE and recompiling solved this problem.



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