Re: Bochs instruction prefetch logic

>However, for the real x86 CPU, the exception shouldn't happen in the
instruction prefetch phase.

 

Why do you think so ?

Please explain your opinion.

Bochs doesn't have speculative prefetch of instruction, it prefetches only
instruction which are about to execute.

So if you see instruction #PF means that instruction fetch had a page fault.

 

Stanislav

 

From: You, Lizhen [mailto:[email protected]] 
Sent: Tuesday, 19 December 2017 10:00
To: [email protected]
Subject: [Bochs-developers] Bochs instruction prefetch logic

 

Hi,

 

I found the Bochs prefetch would hit the Page fault exception as the
stacktrace below. However, for the real x86 CPU, the exception shouldn't
happen in the instruction prefetch phase.

Could anybody help clarify whether the current prefetch logic in Bochs is an
exact emulation of hardware CPU prefetch or not? 

 

(gdb) bt 

#0  BX_CPU_C::write_new_stack_qword (laddr=18446612133333385192, curr_pl=0,
data=514) at ./cpu/access2.cc:1065

#1  0x000000000042830d in BX_CPU_C::long_mode_int (vector=14 '\016',
soft_int=0, push_error=1, error_code=20) at ./cpu/exception.cc:164

#2  0x000000000042989f in BX_CPU_C::interrupt (vector=14 '\016', type=3,
push_error=1, error_code=20) at ./cpu/exception.cc:750

#3  0x0000000000429b7a in BX_CPU_C::exception (vector=14, error_code=20) at
./cpu/exception.cc:944

#4  0x0000000000442531 in BX_CPU_C::page_fault (fault=0,
laddr=139807733655408, user=1, rw=2) at ./cpu/paging.cc:547

#5  0x000000000044275b in BX_CPU_C::translate_linear_long_mode
(laddr=139807733655408, lpf_mask=@0x7fffffffdc9c: 4095, user=1, rw=2)

    at ./cpu/paging.cc:733

#6  0x000000000044350e in BX_CPU_C::translate_linear (tlbEntry=0x88b060
<bx_cpu+12000>, laddr=139807733655408, user=1, rw=2) at ./cpu/paging.cc:1194

#7  0x000000000041c141 in BX_CPU_C::prefetch () at ./cpu/cpu.cc:748

#8  0x000000000041b958 in BX_CPU_C::getICacheEntry () at ./cpu/cpu.cc:338

... 

 

Thanks,

Lizhen

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