Re: Bochs instruction prefetch logic

The problem you describe is similar to x86 code breakpoint set on certain
IP.

Bochs supports that.

Bochs also executes prefetch() after every ICache miss so you just need to
disallow caching in the ICache of this IP + do not allow traces to include
this IP in the middle.

And yes, even this has visible performance impact.

 

From: You, Lizhen [mailto:[email protected]] 
Sent: Thursday, 21 December 2017 4:16
To: Stanislav Shwartsman <[email protected]>;
[email protected]
Subject: RE: [Bochs-developers] Bochs instruction prefetch logic

 

Since We'd like to add some check point before the fetch+execution of
certain EIP, so maybe prefetching one ins a time  would be easier for our
case.

 

Thanks,

Lizhen

 

From: Stanislav Shwartsman [mailto:[email protected]] 
Sent: Thursday, December 21, 2017 12:08 AM
To: You, Lizhen <[email protected] <mailto:[email protected]> >;
[email protected]
<mailto:[email protected]> 
Subject: RE: [Bochs-developers] Bochs instruction prefetch logic

 

Prefetch is on the page boundary.

Why would you have a reason to do so ?

You can read details about how this prefetch works at:

http://bochs.sourceforge.net/How%20the%20Bochs%20works%20under%20the%20hood%
202nd%20edition.pdf

 

 

From: You, Lizhen [mailto:[email protected]] 
Sent: Wednesday, 20 December 2017 8:09
To: You, Lizhen <[email protected] <mailto:[email protected]> >;
Stanislav Shwartsman <[email protected] <mailto:[email protected]> >;
[email protected]
<mailto:[email protected]> 
Subject: RE: [Bochs-developers] Bochs instruction prefetch logic

 

Then what is the boundary of this instruction prefetch in Bochs? Page
boundary? 

And what if I pre-fetch only one instruction one time? Would have big
performance penalty? 

 

Thanks,

Lizhen

 

From: You, Lizhen [mailto:[email protected]] 
Sent: Tuesday, December 19, 2017 8:58 PM
To: Stanislav Shwartsman <[email protected] <mailto:[email protected]> >;
[email protected]
<mailto:[email protected]> 
Subject: Re: [Bochs-developers] Bochs instruction prefetch logic

 

Thanks for the quick reply.  I wrongly took the prefetch in Bochs as the
speculative prefetch of instruction as in hardware. 

 

Thanks,

Lizhen

 

From: Stanislav Shwartsman [mailto:[email protected]] 
Sent: Tuesday, December 19, 2017 8:34 PM
To: You, Lizhen <[email protected] <mailto:[email protected]> >;
[email protected]
<mailto:[email protected]> 
Subject: RE: [Bochs-developers] Bochs instruction prefetch logic

 

>However, for the real x86 CPU, the exception shouldn't happen in the
instruction prefetch phase.

 

Why do you think so ?

Please explain your opinion.

Bochs doesn't have speculative prefetch of instruction, it prefetches only
instruction which are about to execute.

So if you see instruction #PF means that instruction fetch had a page fault.

 

Stanislav

 

From: You, Lizhen [ <mailto:[email protected]>
mailto:[email protected]] 
Sent: Tuesday, 19 December 2017 10:00
To:  <mailto:[email protected]>
[email protected]
Subject: [Bochs-developers] Bochs instruction prefetch logic

 

Hi,

 

I found the Bochs prefetch would hit the Page fault exception as the
stacktrace below. However, for the real x86 CPU, the exception shouldn't
happen in the instruction prefetch phase.

Could anybody help clarify whether the current prefetch logic in Bochs is an
exact emulation of hardware CPU prefetch or not? 

 

(gdb) bt 

#0  BX_CPU_C::write_new_stack_qword (laddr=18446612133333385192, curr_pl=0,
data=514) at ./cpu/access2.cc:1065

#1  0x000000000042830d in BX_CPU_C::long_mode_int (vector=14 '\016',
soft_int=0, push_error=1, error_code=20) at ./cpu/exception.cc:164

#2  0x000000000042989f in BX_CPU_C::interrupt (vector=14 '\016', type=3,
push_error=1, error_code=20) at ./cpu/exception.cc:750

#3  0x0000000000429b7a in BX_CPU_C::exception (vector=14, error_code=20) at
./cpu/exception.cc:944

#4  0x0000000000442531 in BX_CPU_C::page_fault (fault=0,
laddr=139807733655408, user=1, rw=2) at ./cpu/paging.cc:547

#5  0x000000000044275b in BX_CPU_C::translate_linear_long_mode
(laddr=139807733655408, lpf_mask=@0x7fffffffdc9c: 4095, user=1, rw=2)

    at ./cpu/paging.cc:733

#6  0x000000000044350e in BX_CPU_C::translate_linear (tlbEntry=0x88b060
<bx_cpu+12000>, laddr=139807733655408, user=1, rw=2) at ./cpu/paging.cc:1194

#7  0x000000000041c141 in BX_CPU_C::prefetch () at ./cpu/cpu.cc:748

#8  0x000000000041b958 in BX_CPU_C::getICacheEntry () at ./cpu/cpu.cc:338

... 

 

Thanks,

Lizhen

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