Bit 63 of writes to CR3 with PCIDs enabled

Hi,

I noticed what I believe is a discrepancy between the Bochs
implementation of PCIDs and the Intel SDM. Specifically, the Intel SDM
(October 2017 edition) states in §4.10.1.4 that the behaviour of a mov
to CR3 depends on the value of CR4.PCIDE. Specifically, if CR4.PCIDE
is set, then when bit 63 of the value to store in CR3 is set, it can
be treated as a hint to not clear the TLB (or other paging structure
caches).

Since clearing the caches is allowed even when CR4.PCIDE is set and
bit 63 of the value is set, a patch like the attached (which changes
the behaviour of MOV_CR3Rq() before the SetCR3() call) seems to
satisfy the letter of the law.

Thoughts? Am I missing something in the current implementation? :-)

Kent

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