Re: Questions about changing physical address width

According to Intel SDM, this the definition of the reserved bits in 4M page
descriptor:

 

With 32-bit paging, there are reserved bits only if CR4.PSE = 1:

* If the P flag and the PS flag (bit 7) of a PDE are both 1, the bits
reserved depend on MAXPHYADDR, and whether

the PSE-36 mechanism is supported:

― If the PSE-36 mechanism is not supported, bits 21:13 are reserved.

― If the PSE-36 mechanism is supported, bits 21:(MC19) are reserved, where
M is the minimum of 40 and MAXPHYADDR.

* If the PAT is not supported:

― If the P flag of a PTE is 1, bit 7 is reserved.

― If the P flag and the PS flag of a PDE are both 1, bit 12 is reserved.

(If CR4.PSE = 0, no bits are reserved with 32-bit paging.)

 

So the reserved bits check simply should be omitted if physical address is
wider than 40 bits.

I pushed the fix.

 

Thanks,

Stanislav

 

 

From: 探思 [mailto:[email protected]] 
Sent: Thursday, 22 November 2018 4:46
To: bochs-developers <[email protected]>
Cc: ligh429 <[email protected]>; 'leiyu' <[email protected]>; '张
艳林' <[email protected]>; '温冀烨'
<[email protected]>
Subject: [Bochs-developers] Questions about changing physical address width

 

Hi,

 

We want to change Bochs’ physical address width to 46bit.

Could you give us any comments about how to do?

 

Basically, we will change below macro in config.h to 46,

 

#if BX_CPU_LEVEL == 5

  #define BX_PHY_ADDRESS_WIDTH 36

#else

  #define BX_PHY_ADDRESS_WIDTH 40

#endif

 

 

But we also notice code in paging.cc like below

 

const Bit32u PAGING_PDE4M_RESERVED_BITS = ((1 <<
(41-BX_PHY_ADDRESS_WIDTH))-1) << (13 + BX_PHY_ADDRESS_WIDTH - 32);

 

If we change BX_PHY_ADDRESS_WIDTH equal 46,  (41-BX_PHY_ADDRESS_WIDTH) will
be minus. 

What do you think about this?

 

 

Best regards,

--- Cliff

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