issue about SYSRET in Bochs
温冀烨 via bochs-developers <[email protected]> Wed, 17 Apr 2019 08:26:44 +0800
| Newsgroups | gmane.comp.emulators.bochs.devel |
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| Message-ID | <[email protected]> |
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--></style></head><body lang=3DZH-CN link=3Dblue vlink=3D"#954F72"><div cla=
ss=3DWordSection1><p class=3DMsoNormal><span lang=3DEN-US style=3D'font-fam=
ily:"Calibri",sans-serif;color:black'>hi guys: </span><span lang=3DEN-US st=
yle=3D'font-size:12.0pt;font-family:SimSun'><o:p></o:p></span></p><p style=
=3D'text-indent:9.0pt'><span lang=3DEN-US style=3D'font-size:10.5pt;font-fa=
mily:"Calibri",sans-serif'>I found there=E2=80=99s another place different =
between Intel SDM and Bochs code. <o:p></o:p></span></p><p style=3D'text-in=
dent:9.0pt'><span lang=3DEN-US style=3D'font-size:10.5pt;font-family:"Calib=
ri",sans-serif'>Intel SDM states that operating SYSRET will update SS.xxx r=
egisters to specific values (in SDM p1809)<o:p></o:p></span></p><p style=3D=
'text-indent:9.0pt'><span lang=3DEN-US style=3D'font-size:10.5pt;font-famil=
y:"Calibri",sans-serif'>In Bochs, for field base/limit/g/b, such update see=
ms missing . <o:p></o:p></span></p><p style=3D'text-inden=
t:10.5pt'><span lang=3DEN-US style=3D'font-size:10.5pt;font-family:"Calibri=
",sans-serif;color:red'>I tried some modification over it, in bochs2.6.9/cp=
u/proc_ctrl.cc (starts at line 1325) is this a reasonable fix by what=
I meant?<o:p></o:p></span></p><p style=3D'margin-bottom:12.0pt'><span lang=
=3DEN-US style=3D'font-size:10.5pt;font-family:"Calibri",sans-serif'> =
BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.valid =
=3D SegValidCache | SegAccessROK | SegAccessWOK | SegAccessROK4G | SegAcces=
sWOK4G;<br> BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.p&=
nbsp; =3D 1;<br> BX_CPU_THI=
S_PTR sregs[BX_SEG_REG_SS].cache.dpl =3D 3;<br>&nbs=
p; BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.segment =3D 1;&nb=
sp; /* data/code segment */<br> BX_CPU_THIS_PTR sregs[BX_=
SEG_REG_SS].cache.type =3D BX_DATA_READ_WRITE_ACCESSED;<b=
r><span style=3D'color:red'><br> BX_CPU_THIS_PTR sregs[BX=
_SEG_REG_SS].cache.u.segment.base =
=3D 0; /* base address */<br> BX_CPU_THIS_PTR sreg=
s[BX_SEG_REG_SS].cache.u.segment.limit_scaled =3D 0xFFFFFFFF; /* scal=
ed segment limit */<br> BX_CPU_THIS_PTR sregs[BX_SEG_REG_=
SS].cache.u.segment.g =
=3D 1; /* 4k granularity */<br> BX_CPU_THIS_=
PTR sregs[BX_SEG_REG_SS].cache.u.segment.d_b &=
nbsp; =3D 1;</span><o:p></o:p></span></p><p class=3DMsoNo=
rmal><span lang=3DEN-US style=3D'font-size:12.0pt;font-family:SimSun;color:=
black'><o:p> </o:p></span></p><p class=3DMsoNormal><span lang=3DEN-US>=
<o:p> </o:p></span></p><p class=3DMsoNormal><span lang=3DEN-US><o:p>&n=
bsp;</o:p></span></p></div></body></html>=
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